Status Register; Sfr Definition 19.4. Smb0Adr: Smbus0 Address; Sfr Definition 19.5. Smb0Sta: Smbus0 Status - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 19.4. SMB0ADR: SMBus0 Address

R/W R/W
SLV6 SLV5
Bit7 Bit6
Bits7–1: SLV6–SLV0: SMBus0 Slave Address.
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper-
ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address
and corresponds to the first bit of the address byte received.
Bit0: GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.

19.4.5. Status Register

The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 inter-
face. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most
significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at
zero when SI = '1'. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta-
tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code
to service the state or jump to a more extensive service routine).
For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is
logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The
28 SMBus0 states, along with their corresponding status codes, are given in Table 1.1.

SFR Definition 19.5. SMB0STA: SMBus0 Status

R/W R/W
STA7 STA6
Bit7 Bit6
Bits7–3: STA7–STA3: SMBus0 Status Code.
These bits contain the SMBus0 Status Code. There are 28 possible status codes; each sta-
tus code corresponds to a single SMBus state. A valid status code is present in SMB0STA
when the SI flag (SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when
the SI flag is logic 0. Writing to the SMB0STA register at any time will yield indeterminate
results.
Bits2–0: STA2–STA0: The three least significant bits of SMB0STA are always read as logic 0 when
the SI flag is logic 1.
R/W R/W R/W
SLV4 SLV3 SLV2
Bit5 Bit4 Bit3
R/W R/W R/W
STA5 STA4 STA3
Bit5 Bit4 Bit3
R/W R/W
SLV1 SLV0
Bit2 Bit1
SFR Address:
SFR Page:
R/W R/W
STA2 STA1
Bit2 Bit1
Rev. 1.4
R/W Reset Value
GC 00000000
Bit0
0xC3
0
R/W Reset Value
STA0 11111000
Bit0
SFR Address: 0xC1
SFR Page: 0
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