Silicon Labs C8051F130 Manuals

Manuals and User Guides for Silicon Labs C8051F130. We have 1 Silicon Labs C8051F130 manual available for free PDF download: Manual

Silicon Laboratories C8051F130 Manual (350 pages)

8K ISP FLASH MCU

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 4 MB

Table of Contents
3
System Overview

19
- Table 1.1. Product Selection Guide
  20
1 System Overview

21
- Figure 1.1. C8051F120/124 Block Diagram
  21
Absolute Maximum Ratings

38
- Table 2.1. Absolute Maximum Ratings
  38
Global DC Electrical Characteristics

39
- Table 3.1. Global DC Electrical Characteristics
  39
  - (C8051F120/1/2/3 and C8051F130/1/2/3)
    39
  - Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)
    40
Pinout and Package Definitions

41
- Table 4.1. Pin Definitions
  41
4 Pinout and Package Definitions

49
3 Global DC Electrical Characteristics

49
5 ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

55
ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

55
5 ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

72
- Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/5)
  72
6 ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13X Only)

73
ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13X Only)

73
7 ADC2 (8-Bit ADC, C8051F12X Only)

91
ADC2 (8-Bit ADC, C8051F12X Only)

91
7 ADC2 (8-Bit ADC, C8051F12X Only)

103
- Table 7.1. ADC2 Electrical Characteristics
  103
Dacs, 12-Bit Voltage Mode (C8051F12X Only)

105
8 Dacs, 12-Bit Voltage Mode (C8051F12X Only)

105
8 Dacs, 12-Bit Voltage Mode (C8051F12X Only)

111
- Table 8.1. DAC Electrical Characteristics
  111
Voltage Reference

113
- Reference Configuration on the C8051F120/2/4/6
  113
9 Voltage Reference

114
9 Voltage Reference

118
- Table 9.1. Voltage Reference Electrical Characteristics
  118
10 Comparators

119
Comparators

119
10 Comparators

126
- Table 10.1. Comparator Electrical Characteristics
  126
Microcontroller

127
11 CIP-51 Microcontroller

128
- Figure 11.1. CIP-51 Block Diagram
  128
  - Instruction Set
    129
    
    Instruction and CPU Timing
    129
    
    MOVX Instruction and Program Memory
    129
    
    Table 11.1. CIP-51 Instruction Set Summary
    129
  - Memory Organization
    133
    
    Program Memory
    133
    
    Figure 11.2. Memory Map
    133
    
    Figure 11.3. Address Memory Map for Instruction Fetches (128 Kb Flash Only)
    134
11 CIP-51 Microcontroller

129
12 Multiply and Accumulate (MAC0)

165
Multiply and Accumulate (MAC0)

165
12 Multiply and Accumulate (MAC0)

168
13 Reset Sources

177
Reset Sources

177
- Figure 13.1. Reset Sources
  177
  - Power-On Reset
    178
  - Power-Fail Reset
    178
  - Figure 13.2. Reset Timing
    178
  - External Reset
    179
  - Missing Clock Detector Reset
    179
  - Comparator0 Reset
    179
  - External CNVSTR0 Pin Reset
    179
  - Watchdog Timer Reset
    179
    
    Enable/Reset WDT
    180
    
    Disable WDT
    180
    
    Disable WDT Lockout
    180
    
    Setting WDT Interval
    180
- SFR Definition 13.1. WDTCN: Watchdog Timer Control
  181
- SFR Definition 13.2. RSTSRC: Reset Source
  182
13 Reset Sources

183
- Table 13.1. Reset Electrical Characteristics
  183
14 Oscillators

185
14 Oscillators

185
Oscillators

185
Flash Memory

199
- Programming the Flash Memory
  199
15 Flash Memory

200
15 Flash Memory

201
16 Branch Target Cache

211
Branch Target Cache

211
External Data Memory Interface and On-Chip XRAM

219
- Accessing XRAM
  219
  - 16-Bit MOVX Example
    219
- Configuring the External Memory Interface
  219
- Port Selection and Configuration
  220
- SFR Definition 17.1. EMI0CN: External Memory Interface Control
  220
- SFR Definition 17.2. EMI0CF: External Memory Configuration
  221
  - Multiplexed and Non-Multiplexed Selection
    222
    
    Multiplexed Configuration
    222
    
    Figure 17.1. Multiplexed Configuration Example
    222
    
    Non-Multiplexed Configuration
    223
    
    Figure 17.2. Non-Multiplexed Configuration Example
    223
  - Memory Mode Selection
    224
    
    Internal XRAM Only
    224
    
    Split Mode Without Bank Select
    224
    
    Figure 17.3. EMIF Operating Modes
    224
    
    Split Mode with Bank Select
    225
    
    External Only
    225
  - EMIF Timing
    225
17 External Data Memory Interface and On-Chip XRAM

222
- SFR Definition 17.3. EMI0TC: External Memory Timing Control
  226
17 External Data Memory Interface and On-Chip XRAM

233
16 Branch Target Cache

233
- Table 17.1. AC Parameters for External Memory Interface
  233
18 Port Input/Output

235
Port Input/Output

235
- Figure 18.1. Port I/O Cell Block Diagram
  235
18 Port Input/Output

236
19 System Management Bus / I2C Bus (Smbus0)

259
System Management Bus / I2C Bus (Smbus0)

259
- Figure 19.1. Smbus0 Block Diagram
  259
  - Supporting Documents
    260
  - Smbus Protocol
    260
    
    Figure 19.2. Typical Smbus Configuration
    260
    
    Arbitration
    261
    
    Clock Low Extension
    261
    
    Figure 19.3. Smbus Transaction
    261
    
    SCL High (Smbus Free) Timeout
    261
    
    SCL Low Timeout
    261
  - Smbus Transfer Modes
    262
    
    Master Transmitter Mode
    262
    
    Master Receiver Mode
    262
    
    Figure 19.4. Typical Master Transmitter Sequence
    262
    
    Figure 19.5. Typical Master Receiver Sequence
    262
    
    Slave Transmitter Mode
    263
    
    Slave Receiver Mode
    263
    
    Figure 19.6. Typical Slave Transmitter Sequence
    263
    
    Figure 19.7. Typical Slave Receiver Sequence
    263
  - Smbus Special Function Registers
    264
    
    Control Register
    264
- SFR Definition 19.1. SMB0CN: Smbus0 Control
  266
  - Clock Rate Register
    267
- SFR Definition 19.2. SMB0CR: Smbus0 Clock Rate
  267
  - Data Register
    268
  - Address Register
    268
- SFR Definition 19.3. SMB0DAT: Smbus0 Data
  268
  - Status Register
    269
- SFR Definition 19.4. SMB0ADR: Smbus0 Address
  269
- SFR Definition 19.5. SMB0STA: Smbus0 Status
  269
19 System Management Bus / I2C Bus (Smbus0)

270
- Table 19.1. SMB0STA Status Codes and States
  270
20 Enhanced Serial Peripheral Interface (SPI0)

273
Enhanced Serial Peripheral Interface (SPI0)

273
20 Enhanced Serial Peripheral Interface (SPI0)

285
- Table 20.1. SPI Slave Timing Parameters
  285
21 Uart0

287
Uart0

287
- Figure 21.1. UART0 Block Diagram
  287
21 Uart0

288
22 Uart1

299
Uart1

299
- Figure 22.1. UART1 Block Diagram
  299
  - Enhanced Baud Rate Generation
    300
  - Figure 22.2. UART1 Baud Rate Logic
    300
  - Operational Modes
    301
    
    8-Bit UART
    301
    
    Figure 22.3. UART Interconnect Diagram
    301
    
    Figure 22.4. 8-Bit UART Timing Diagram
    301
    
    9-Bit UART
    302
    
    Figure 22.5. 9-Bit UART Timing Diagram
    302
  - Multiprocessor Communications
    303
  - Figure 22.6. UART Multi-Processor Mode Interconnect Diagram
    303
- SFR Definition 22.1. SCON1: Serial Port 1 Control
  304
22 Uart1

305
- Table 22.1. Timer Settings for Standard Baud Rates
  305
  - Using the Internal 24.5 Mhz Oscillator
    305
- SFR Definition 22.2. SBUF1: Serial (UART1) Port Data Buffer
  305
Timers

309
- Timer 0 and Timer 1
  309
23 Timers

310
24 Programmable Counter Array

325
Programmable Counter Array

325
- Figure 24.1. PCA Block Diagram
  325
24 Programmable Counter Array

326
23 Timers

326
Jtag (Ieee 1149.1)

341
- JTAG Register Definition 25.1. IR: JTAG Instruction Register
  341
  - Boundary Scan
    342
    
    Table 25.1. Boundary Data Register Bit Definitions
    342
    
    BYPASS Instruction
    343
    
    EXTEST Instruction
    343
    
    IDCODE Instruction
    343
    
    SAMPLE Instruction
    343
25 Jtag (Ieee 1149.1)

342
Document Change List

349
Contact Information

350

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Silicon Labs C8051F130 Manuals

Silicon Laboratories C8051F130 Manual (350 pages)

Table of Contents

System Overview

1 System Overview

Absolute Maximum Ratings

Global DC Electrical Characteristics

Pinout and Package Definitions

4 Pinout and Package Definitions

3 Global DC Electrical Characteristics

5 ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

5 ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)

6 ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13X Only)

ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13X Only)

7 ADC2 (8-Bit ADC, C8051F12X Only)

ADC2 (8-Bit ADC, C8051F12X Only)

7 ADC2 (8-Bit ADC, C8051F12X Only)

Dacs, 12-Bit Voltage Mode (C8051F12X Only)

8 Dacs, 12-Bit Voltage Mode (C8051F12X Only)

8 Dacs, 12-Bit Voltage Mode (C8051F12X Only)

Voltage Reference

9 Voltage Reference

9 Voltage Reference

10 Comparators

Comparators

10 Comparators

Microcontroller

11 CIP-51 Microcontroller

11 CIP-51 Microcontroller

12 Multiply and Accumulate (MAC0)

Multiply and Accumulate (MAC0)

12 Multiply and Accumulate (MAC0)

13 Reset Sources

Reset Sources

13 Reset Sources

14 Oscillators

14 Oscillators

Oscillators

Flash Memory

15 Flash Memory

15 Flash Memory

16 Branch Target Cache

Branch Target Cache

External Data Memory Interface and On-Chip XRAM

17 External Data Memory Interface and On-Chip XRAM

17 External Data Memory Interface and On-Chip XRAM

16 Branch Target Cache

18 Port Input/Output

Port Input/Output

18 Port Input/Output

19 System Management Bus / I2C Bus (Smbus0)

System Management Bus / I2C Bus (Smbus0)

19 System Management Bus / I2C Bus (Smbus0)

20 Enhanced Serial Peripheral Interface (SPI0)

Enhanced Serial Peripheral Interface (SPI0)

20 Enhanced Serial Peripheral Interface (SPI0)

21 Uart0

Uart0

21 Uart0

22 Uart1

Uart1

22 Uart1

Timers

23 Timers

24 Programmable Counter Array

Programmable Counter Array

24 Programmable Counter Array

23 Timers

Jtag (Ieee 1149.1)

25 Jtag (Ieee 1149.1)

Document Change List

Contact Information

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