Sfr Definition 7.3. Adc2Cf: Adc2 Configuration - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 7.3. ADC2CF: ADC2 Configuration

2
SFR Page:
0xBC
SFR Address:
R/W R/W
AD2SC4 AD2SC3 AD2SC2
Bit7 Bit6
Bits7–3: AD2SC4–0: ADC2 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD2SC refers to the 5-bit value held in AD2SC4–0, and CLK
ADC2 SAR clock (Note: the ADC2 SAR Conversion Clock should be less than or equal to
6 MHz).
SYSCLK
---------------------- - 1
AD2SC =
CLK
Bit2: UNUSED. Read = 0b; Write = don't care.
Bits1–0: AMP2GN1–0: ADC2 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
R/W R/W R/W
AD2SC1 AD2SC0
Bit5 Bit4 Bit3
–
SAR2
Rev. 1.4
R/W R/W R/W
- AMP2GN1 AMP2GN0 11111000
Bit2 Bit1 Bit0
refers to the desired
SAR2
Reset Value
97