Figure 20.6. Slave Mode Data/Clock Timing (Ckpha = 0); Figure 20.7. Slave Mode Data/Clock Timing (Ckpha = 1) - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)

Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)

SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MISO
NSS (4-Wire Mode)

Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)

MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Rev. 1.4
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
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