Sfr Definition 18.19. P7: Port7 Data; Sfr Definition 18.20. P7Mdout: Port7 Output Mode - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
P7.7 P7.6
Bit7 Bit6
Bits7–0: P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P7MDOUT bit = 0). See SFR Definition
18.20.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
Note: P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See
Interface and On-Chip XRAM" on page 219
Interface.

SFR Definition 18.20. P7MDOUT: Port7 Output Mode

R/W R/W
Bit7 Bit6
Bits7–0: P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

SFR Definition 18.19. P7: Port7 Data

R/W R/W R/W
P7.5 P7.4 P7.3
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W
P7.2 P7.1
Bit2 Bit1
SFR Address:
SFR Page:
Section "17. External Data Memory
for more information about the External Memory
R/W R/W
Bit2 Bit1
SFR Address:
SFR Page:
R/W Reset Value
P7.0 11111111
Bit
Bit0
Addressable
0xF8
F
R/W Reset Value
00000000
Bit0
0x9F
F
257