Silicon Laboratories C8051F12 Series Manual page 47

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Pin Numbers
'F120
Name
'F122
'F124
'F126
A8m/A0/P6.0 80
A9m/A1/P6.1 79
A10m/A2/P6.2 78
A11m/A3/P6.3 77
A12m/A4/P6.4 76
A13m/A5/P6.5 75
A14m/A6/P6.6 74
A15m/A7/P6.7 73
AD0/D0/P7.0 72
AD1/D1/P7.1 71
AD2/D2/P7.2 70
AD3/D3/P7.3 69
AD4/D4/P7.4 68
Table 4.1. Pin Definitions (Continued)
'F121 'F130 'F131
Type
'F123 'F132 'F133
'F125
'F127
80 D I/O Bit 8 External Memory Address bus (Multiplexed
79 D I/O Port 6.1. See Port Input/Output section for com-
78 D I/O Port 6.2. See Port Input/Output section for com-
77 D I/O Port 6.3. See Port Input/Output section for com-
76 D I/O Port 6.4. See Port Input/Output section for com-
75 D I/O Port 6.5. See Port Input/Output section for com-
74 D I/O Port 6.6. See Port Input/Output section for com-
73 D I/O Port 6.7. See Port Input/Output section for com-
72 D I/O Bit 0 External Memory Address/Data bus (Multi-
71 D I/O Port 7.1. See Port Input/Output section for com-
70 D I/O Port 7.2. See Port Input/Output section for com-
69 D I/O Port 7.3. See Port Input/Output section for com-
68 D I/O Port 7.4. See Port Input/Output section for com-
Description
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 6.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plexed mode)
Bit 0 External Memory Data bus (Non-multi-
plexed mode)
Port 7.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
Rev. 1.4 47