Figure 1.5. C8051F130/132 Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
VDD
VDD
VDD
Digital Power
DGND
DGND
DGND
AV+
AV+
Analog Power
AGND
AGND
TCK
Boundary Scan
JTAG
TMS
TDI Logic
Debug HW
TDO
RST
VDD
WDT
MONEN
Monitor
External Oscillator
XTAL1
Circuit
XTAL2
PLL
Circuitry
Calibrated Internal
Oscillator
VREF VREF
VREF0
AIN0.0
AIN0.1
AIN0.2
A
AIN0.3
M Prog
AIN0.4
Gain
U
AIN0.5
X
AIN0.6
AIN0.7
TEMP
SENSOR
CP0+
CP0
CP0-
CP1+
CP1
CP1-

Figure 1.5. C8051F130/132 Block Diagram

SFR Bus
8
256 byte
0
RAM
5
8kbyte
Reset
XRAM
1
External Data
Memory Bus
C
System
Clock
o
FLASH
128kbyte
r
('F130)
64kbyte
e
('F132)
64x4 byte
cache
ADC
100ksps
(10-Bit)
Rev. 1.4
Port I/O
Config.
UART0
P0
Drv
UART1
C
SMBus
R
P1
SPI Bus
O
Drv
PCA
S
S
Timers 0,
P2
1, 2, 4
B
Drv
A
Timer 3/
RTC
R
P3
P0, P1,
Drv
P2, P3
Latches
Crossbar
Config.
C
P4 Latch
Bus Control
T
L
P5 Latch
A
Address Bus
d
d P6 Latch
r
D
P7 Latch
Data Bus
a
t
a
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4
P4.4
P4.5/ALE
DRV
P4.6/RD
P4.7/WR
P5.0/A8
P5
DRV
P5.7/A15
P6.0/A0
P6
DRV
P6.7/A7
P7.0/D0
P7
DRV
P7.7/D7
25