Silicon Laboratories C8051F12 Series Manual page 43

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
'F120
Name
'F122
'F124
'F126
DAC1 99
P0.0 62
P0.1 61
P0.2 60
P0.3 59
P0.4 58
ALE/P0.5 57
RD/P0.6 56
WR/P0.7 55
AIN2.0/A8/P1.0 36
AIN2.1/A9/P1.1 35
Table 4.1. Pin Definitions (Continued)
Pin Numbers
'F121 'F130 'F131
Type
'F123 'F132 'F133
'F125
'F127
63 A Out Digital to Analog Converter 1 Voltage Output.
55 62 55 D I/O Port 0.0. See Port Input/Output section for com-
54 61 54 D I/O Port 0.1. See Port Input/Output section for com-
53 60 53 D I/O Port 0.2. See Port Input/Output section for com-
52 59 52 D I/O Port 0.3. See Port Input/Output section for com-
51 58 51 D I/O Port 0.4. See Port Input/Output section for com-
50 57 50 D I/O ALE Strobe for External Memory Address bus
49 56 49 D I/O /RD Strobe for External Memory Address bus
48 55 48 D I/O /WR Strobe for External Memory Address bus
29 36 29 A In
D I/O
28 35 28 A In
D I/O
Description
(See DAC Specification for complete descrip-
tion).
plete description.
plete description.
plete description.
plete description.
plete description.
(multiplexed mode)
Port 0.5
See Port Input/Output section for complete
description.
Port 0.6
See Port Input/Output section for complete
description.
Port 0.7
See Port Input/Output section for complete
description.
ADC2 Input Channel 0 (See ADC2 Specification
for complete description).
Bit 8 External Memory Address bus (Non-multi-
plexed mode)
Port 1.0
See Port Input/Output section for complete
description.
Port 1.1. See Port Input/Output section for com-
plete description.
Rev. 1.4 43