Silicon Laboratories C8051F12 Series Manual page 12

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 276
Figure 20.5. Master Mode Data/Clock Timing ........................................................ 278
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 279
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 279
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 283
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 283
Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 284
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 284
21. UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 287
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 288
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 288
Figure 21.4. UART0 Mode 1 Timing Diagram ....................................................... 289
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 291
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 292
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 294
22. UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 299
Figure 22.2. UART1 Baud Rate Logic .................................................................... 300
Figure 22.3. UART Interconnect Diagram .............................................................. 301
Figure 22.4. 8-Bit UART Timing Diagram.............................................................. 301
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 302
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 303
23. Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 310
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 311
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 312
Figure 23.4. T2, 3, and 4 Capture Mode Block Diagram ........................................ 318
Figure 23.5. Tn Auto-reload (T2,3,4) and Toggle Mode (T2,4) Block Diagram ..... 319
24. Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 325
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 326
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 328
Figure 24.4. PCA Capture Mode Diagram.............................................................. 329
Figure 24.5. PCA Software Timer Mode Diagram .................................................. 330
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 331
Figure 24.7. PCA Frequency Output Mode ............................................................ 332
Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................... 333
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 334
25. JTAG (IEEE 1149.1)
12 Rev. 1.4