Port Selection And Configuration; Sfr Definition 17.1. Emi0Cn: External Memory Interface Control - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
5. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
select, or off-chip only).
6. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 17.2.

17.3. Port Selection and Configuration

The External Memory Interface can appear on Ports 3, 2, 1, and 0 (All Devices) or on Ports 7, 6, 5, and 4
(100-pin TQFP devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are
selected, the EMIFLE bit (XBR2.1) must be set to a '1' so that the Crossbar will skip over P0.7 (/WR), P0.6
(/RD), and if multiplexed mode is selected P0.5 (ALE). For more information about the configuring the
Crossbar, see Section "18.1. Ports 0 through 3 and the Priority Crossbar Decoder" on page 238
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar (on Ports 3, 2, 1, and 0). See
Output" on page 235 for more information about the Crossbar and Port operation and configuration. The
Port latches should be explicitly configured to 'park' the External Memory Interface pins in a dor-
mant state, most commonly by setting them to a logic 1 .
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode. See"Configuring the Output
Modes of the Port Pins" on page 239.

SFR Definition 17.1. EMI0CN: External Memory Interface Control

R/W R/W
PGSEL7 PGSEL6
Bit7 Bit6
Bits7–0: PGSEL[7:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
220
R/W R/W
PGSEL5 PGSEL4 PGSEL3
Bit5 Bit4
Rev. 1.4
R/W R/W R/W
PGSEL2 PGSEL1
Bit3 Bit2 Bit1
.
Section "18. Port Input/
R/W Reset Value
PGSEL0 00000000
Bit0
SFR Address: 0xA2
SFR Page: 0