Silicon Laboratories C8051F12 Series Manual page 44

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
'F120
Name
'F122
'F124
'F126
AIN2.2/A10/P1.2 34
AIN2.3/A11/P1.3 33
AIN2.4/A12/P1.4 32
AIN2.5/A13/P1.5 31
AIN2.6/A14/P1.6 30
AIN2.7/A15/P1.7 29
A8m/A0/P2.0 46
A9m/A1/P2.1 45
A10m/A2/P2.2 44
A11m/A3/P2.3 43
A12m/A4/P2.4 42
A13m/A5/P2.5 41
A14m/A6/P2.6 40
A15m/A7/P2.7 39
44
Table 4.1. Pin Definitions (Continued)
Pin Numbers
'F121 'F130 'F131
Type
'F123 'F132 'F133
'F125
'F127
27 34 27 A In
D I/O
26 33 26 A In
D I/O
23 32 23 A In
D I/O
22 31 22 A In
D I/O
21 30 21 A In
D I/O
20 29 20 A In
D I/O
37 46 37 D I/O Bit 8 External Memory Address bus (Multiplexed
36 45 36 D I/O Port 2.1. See Port Input/Output section for com-
35 44 35 D I/O Port 2.2. See Port Input/Output section for com-
34 43 34 D I/O Port 2.3. See Port Input/Output section for com-
33 42 33 D I/O Port 2.4. See Port Input/Output section for com-
32 41 32 D I/O Port 2.5. See Port Input/Output section for com-
31 40 31 D I/O Port 2.6. See Port Input/Output section for com-
30 39 30 D I/O Port 2.7. See Port Input/Output section for com-
Rev. 1.4
Description
Port 1.2. See Port Input/Output section for com-
plete description.
Port 1.3. See Port Input/Output section for com-
plete description.
Port 1.4. See Port Input/Output section for com-
plete description.
Port 1.5. See Port Input/Output section for com-
plete description.
Port 1.6. See Port Input/Output section for com-
plete description.
Port 1.7. See Port Input/Output section for com-
plete description.
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 2.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.