External Interrupts; Table 11.4. Interrupt Summary - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

11.3.2. External Interrupts

Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or
active-low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0
(TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin.
The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request
will be generated.
Interrupt Source
Reset
External Interrupt 0 (/INT0) 0x0003
Timer 0 Overflow
External Interrupt 1 (/INT1) 0x0013
Timer 1 Overflow
UART0
Timer 2
Serial Peripheral Interface 0x0033
SMBus Interface
ADC0 Window Comparator 0x0043
Programmable Counter
Array
Comparator 0 Falling Edge 0x0053
Comparator 0 Rising Edge 0x005B
Comparator 1 Falling Edge 0x0063

Table 11.4. Interrupt Summary

Interru
Priority
pt Pending Flags
Order
Vector
0x0000 Top None
0 IE0 (TCON.1)
0x000B 1 TF0 (TCON.5)
2 IE1 (TCON.3)
0x001B 3 TF1 (TCON.7)
RI0 (SCON0.0)
0x0023 4
TI0 (SCON0.1)
TF2 (TMR2CN.7)
0x002B 5
EXF2 (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
6
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
0x003B 7 SI (SMB0CN.3)
AD0WINT
8
(ADC0CN.1)
CF (PCA0CN.7)
0x004B 9
CCFn (PCA0CN.n)
10 CP0FIF (CPT0CN.4)
11 CP0RIF (CPT0CN.5)
12 CP1FIF (CPT1CN.4)
Rev. 1.4
Enable
Flag
Always
N/A N/A 0
Enabled
Y Y 0 EX0 (IE.0) PX0 (IP.0)
Y Y 0 ET0 (IE.1) PT0 (IP.1)
Y Y 0 EX1 (IE.2) PX1 (IP.2)
Y Y 0 ET1 (IE.3) PT1 (IP.3)
Y 0 ES0 (IE.4) PS0 (IP.4)
Y 0 ET2 (IE.5) PT2 (IP.5)
ESPI0
Y 0
(EIE1.0)
ESMB0
Y 0
(EIE1.1)
EWADC0
Y 0
(EIE1.2)
EPCA0
Y 0
(EIE1.3)
ECP0F
Y 1
(EIE1.4)
ECP0R
Y 1
(EIE1.5)
ECP1F
Y 2
(EIE1.6)
Priority
Control
Always
Highest
PSPI0
(EIP1.0)
PSMB0
(EIP1.1)
PWADC0
(EIP1.2)
PPCA0
(EIP1.3)
PCP0F
(EIP1.4)
PCP0R
(EIP1.5)
PCP1F
(EIP1.6)
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