Uart0 Operational Modes; Mode 0: Synchronous Mode; Figure 21.2. Uart0 Mode 0 Timing Diagram; Figure 21.3. Uart0 Mode 0 Interconnect - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

21.1. UART0 Operational Modes

UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON0 register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 21.1.
Mode Synchronization
0 Synchronous
1 Asynchronous
2 Asynchronous
3 Asynchronous

21.1.1. Mode 0: Synchronous Mode

Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX0 pin. The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 21.3).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are
transferred LSB first (see the timing diagram in Figure 21.2), and the TI0 Transmit Interrupt Flag
(SCON0.1) is set at the end of the eighth bit time. Data reception begins when the REN0 Receive Enable
bit (SCON0.4) is set to logic 1 and the RI0 Receive Interrupt Flag (SCON0.0) is cleared. One cycle after
the eighth bit is shifted in, the RI0 flag is set and reception stops until software clears the RI0 bit. An inter-
rupt will occur if enabled when either TI0 or RI0 are set.
The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pullup will
typically be required.
RX (data out)
TX (clk out)
RX (data in)
TX (clk out)

Figure 21.2. UART0 Mode 0 Timing Diagram

288

Table 21.1. UART0 Modes

Baud Clock
SYSCLK / 12
Timer 1, 2, 3, or 4 Overflow
SYSCLK / 32 or SYSCLK / 64
Timer 1, 2, 3, or 4 Overflow
MODE 0 TRANSMIT
D0 D1 D2
MODE 0 RECEIVE
D0 D1 D2
TX
C8051Fxxx
RX

Figure 21.3. UART0 Mode 0 Interconnect

Rev. 1.4
Data Bits
8
8
9
9
D3 D4 D5 D6 D7
D3 D4 D5 D6
CLK
Shift
Reg.
DATA
8 Extra Outputs
Start/Stop Bits
None
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
D7