Silicon Laboratories C8051F12 Series Manual page 46

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
'F120
Name
'F122
'F124
'F126
ALE/P4.5 93
RD/P4.6 92
WR/P4.7 91
A8/P5.0 88
A9/P5.1 87
A10/P5.2 86
A11/P5.3 85
A12/P5.4 84
A13/P5.5 83
A14/P5.6 82
A15/P5.7 81
46
Table 4.1. Pin Definitions (Continued)
Pin Numbers
'F121 'F130 'F131
Type
'F123 'F132 'F133
'F125
'F127
93 D I/O ALE Strobe for External Memory Address bus
92 D I/O /RD Strobe for External Memory Address bus
91 D I/O /WR Strobe for External Memory Address bus
88 D I/O Bit 8 External Memory Address bus (Non-multi-
87 D I/O Port 5.1. See Port Input/Output section for com-
86 D I/O Port 5.2. See Port Input/Output section for com-
85 D I/O Port 5.3. See Port Input/Output section for com-
84 D I/O Port 5.4. See Port Input/Output section for com-
83 D I/O Port 5.5. See Port Input/Output section for com-
82 D I/O Port 5.6. See Port Input/Output section for com-
81 D I/O Port 5.7. See Port Input/Output section for com-
Rev. 1.4
Description
(multiplexed mode)
Port 4.5
See Port Input/Output section for complete
description.
Port 4.6
See Port Input/Output section for complete
description.
Port 4.7
See Port Input/Output section for complete
description.
plexed mode)
Port 5.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.