Sfr Definition 23.3. Ckcon: Clock Control; Sfr Definition 23.4. Tl0: Timer 0 Low Byte - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 23.3. CKCON: Clock Control

R/W R/W
- -
Bit7 Bit6
Bits7–5: UNUSED. Read = 000b, Write = don't care.
Bit4: T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
Bit3: T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2: UNUSED. Read = 0b, Write = don't care.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1
0
0
1
1
*Note: External clock divided by 8 is synchronized with the system
clock, and external clock must be less than or equal to the
system clock frequency to operate the timer in this mode.

SFR Definition 23.4. TL0: Timer 0 Low Byte

R/W R/W
Bit7 Bit6
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
R/W R/W R/W
- T1M T0M
Bit5 Bit4 Bit3
SCA0 Prescaled Clock
0 System clock divided by 12
1 System clock divided by 4
0 System clock divided by 48
1 External clock divided by 8*
R/W R/W R/W
Bit5 Bit4 Bit3
R/W R/W
- SCA1
Bit2 Bit1
R/W R/W
Bit2 Bit1
Rev. 1.4
R/W Reset Value
SCA0 00000000
Bit0
0x8E
SFR Address:
0
SFR Page:
R/W Reset Value
00000000
Bit0
0x8A
SFR Address:
SFR Page: 0
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