Register Descriptions; Sfr Definition 11.6. Sp: Stack Pointer; Sfr Definition 11.7. Dpl: Data Pointer Low Byte; Sfr Definition 11.8. Dph: Data Pointer High Byte - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

11.2.7. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
R/W R/W
Bit7 Bit6
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.

SFR Definition 11.7. DPL: Data Pointer Low Byte

R/W R/W
Bit7 Bit6
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.

SFR Definition 11.8. DPH: Data Pointer High Byte

R/W R/W
Bit7 Bit6
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.

SFR Definition 11.6. SP: Stack Pointer

R/W R/W R/W
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Reset Value
00000111
0x81
All Pages
Reset Value
00000000
0x82
All Pages
Reset Value
00000000
0x83
All Pages
151