Settling Time Requirements; Figure 7.3. Adc2 Equivalent Input Circuit - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

7.2.3. Settling Time Requirements

A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis-
tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit.
The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1.
Note: An absolute minimum settling time of 800 ns required after any MUX selection. In low-power tracking
mode, three SAR2 clocks are used for tracking at the start of every conversion. For most applications,
these three SAR2 clocks will meet the tracking requirements.
Equation 7.1. ADC2 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R is the sum of the ADC2 MUX resistance and any external source resistance.
TOTAL
n is the ADC resolution in bits (8).
Differential Mode
MUX Select
AIN2.x
R
MUX
RC = R * C
Input MUX
AIN2.y
R
MUX
MUX Select
94
n
 
2
×
------ -
t = ln
 
SA
= 5k
C = 5pF
SAMPLE
SAMPLE
C = 5pF
SAMPLE
= 5k
Note: When the PGA gain is set to 0.5, C

Figure 7.3. ADC2 Equivalent Input Circuit

Rev. 1.4
R C
TOTAL SAMPLE
Single-Ended Mode
MUX Select
AIN2.x
R
RC = R
Input MUX
= 3pF
SAMPLE
= 5k
MUX
C = 5pF
SAMPLE
* C
SAMPLE