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ANALOG PERIPHERALS
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SAR ADC
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12-Bit (C8051F120/1/4/5)
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10-Bit (C8051F122/3/6/7)
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± 1 LSB INL
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Programmable Throughput up to 100 ksps
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Up to 8 External Inputs; Programmable as Single-Ended or
Differential
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Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
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Data-Dependent Windowed Interrupt Generator
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Built-in Temperature Sensor
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8-bit ADC
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Programmable Throughput up to 500 ksps
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8 External Inputs (Single-Ended or Differential)
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Programmable Amplifier Gain: 4, 2, 1, 0.5
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Two 12-bit DACs
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Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
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Two Analog Comparators
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Voltage Reference
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VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
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On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
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Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
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Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
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IEEE1149.1 Compliant Boundary Scan
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Complete Development Kit
Preliminary Rev. 1.2 12/03
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
High-Speed Mixed-Signal ISP FLASH MCU Family
HIGH SPEED 8051 µC CORE
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MEMORY
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DIGITAL PERIPHERALS
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CLOCK SOURCES
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POWER SUPPLIES
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100-PIN TQFP OR 64-PIN TQFP PACKAGING
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ANALOG PERIPHERALS
TEMP
SENSOR
10/12-bit
100ksps
PGA
ADC
VREF
8-bit
500ksps
PGA
ADC
12-Bit
DAC
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+
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12-Bit
VOLTAGE
DAC
COMPARATORS
HIGH-SPEED CONTROLLER CORE
8051 CPU
128KB
(50 or 100MIPS)
ISP FLASH
20
DEBUG
INTERRUPTS
CIRCUITRY
Copyright © 2003 by Silicon Laboratories
C8051F120/1/2/3/4/5/6/7
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
Up to 100 MIPS (C8051F120/1/2/3) or 50 MIPS
(C8051F124/5/6/7) Throughput using Integrated PLL
2-cycle 16 x 16 MAC Engine (C8051F120/1/2/3)
Flexible Interrupt Sources
8448 Bytes Internal Data RAM (8k + 256)
128k Bytes Banked FLASH; In-System programmable in
1024-byte Sectors
External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
8 Byte-Wide Port I/O (C8051F120/2/4/6); 5V tolerant
4 Byte-Wide Port I/O (C8051F121/3/5/7); 5V tolerant
2
Hardware SMBus™ (I
C™ Compatible), SPI™, and
Two UART Serial Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with
6 Capture/Compare Modules
5 General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer; Bi-directional Reset Pin
Internal Precision Oscillator: 24.5 MHz
Flexible PLL technology
External Oscillator: Crystal, RC, C, or Clock
Supply Range: 2.7-3.6V (50 MIPS) 3.0-3.6V (100 MIPS)
Power Saving Sleep and Shutdown Modes
Temperature Range: -40°C to +85°C
DIGITAL I/O
UART0
Port 0
UART1
Port 1
SMBus
Port 2
SPI Bus
PCA
Port 3
Timer 0
Timer 1
Port 4
Timer 2
Port 5
Timer 3
Port 6
Timer 4
Port 7
64 pin
100 pin
8448 B
16 x 16 MAC
SRAM
('F120/1/2/3)
CLOCK / PLL
JTAG
CIRCUIT
C8051F120/1/2/3/4/5/6/7-DS12
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Related Manuals for Silicon Laboratories C8051F120
Summary of Contents for Silicon Laboratories C8051F120
- Page 1 SAR ADC Pipelined Instruction Architecture; Executes 70% of • Instruction Set in 1 or 2 System Clocks 12-Bit (C8051F120/1/4/5) Up to 100 MIPS (C8051F120/1/2/3) or 50 MIPS • 10-Bit (C8051F122/3/6/7) (C8051F124/5/6/7) Throughput using Integrated PLL • ± 1 LSB INL 2-cycle 16 x 16 MAC Engine (C8051F120/1/2/3) •...
- Page 2 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
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Page 3: Table Of Contents
1.10.Comparators and DACs....................35 2. ABSOLUTE MAXIMUM RATINGS ..................36 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ............37 4. PINOUT AND PACKAGE DEFINITIONS................39 5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) ..............49 5.1. Analog Multiplexer and PGA..................49 5.2. ADC Modes of Operation ....................51 5.2.1. Starting a Conversion.....................51 5.2.2. - Page 4 C8051F120/1/2/3/4/5/6/7 8.1.1. Update Output On-Demand ...................99 8.1.2. Update Output Based on Timer Overflow ............100 8.2. DAC Output Scaling/Justification.................100 9. VOLTAGE REFERENCE (C8051F120/2/4/6) ..............107 10. VOLTAGE REFERENCE (C8051F121/3/5/7) ..............109 11. COMPARATORS........................111 12. CIP-51 MICROCONTROLLER..................119 12.1.Instruction Set........................120 12.1.1. Instruction and CPU Timing................120 12.1.2.
- Page 5 C8051F120/1/2/3/4/5/6/7 14.7. Watchdog Timer Reset ....................169 14.7.1. Enable/Reset WDT ....................169 14.7.2. Disable WDT .......................170 14.7.3. Disable WDT Lockout..................170 14.7.4. Setting WDT Interval...................170 15. OSCILLATORS........................173 15.1.Programmable Internal Oscillator .................173 15.2.External Oscillator Drive Circuit...................175 15.3.System Clock Selection....................175 15.4. External Crystal Example....................177 15.5.External RC Example ....................177 15.6.
- Page 6 19.1.5. Configuring Port 1 Pins as Analog Inputs ............219 19.1.6. External Memory Interface Pin Assignments ............220 19.1.7. Crossbar Pin Assignment Example..............222 19.2. Ports 4 through 7 (C8051F120/2/4/6 only) ..............231 19.2.1. Configuring Ports which are not Pinned Out............231 19.2.2. Configuring the Output Modes of the Port Pins ..........231 19.2.3.
- Page 7 C8051F120/1/2/3/4/5/6/7 21.5.Serial Clock Timing ......................254 21.6. SPI Special Function Registers ..................256 22. UART0 ..........................263 22.1.UART0 Operational Modes ..................264 22.1.1. Mode 0: Synchronous Mode................264 22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate ............265 22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............266 22.1.4.
- Page 8 C8051F120/1/2/3/4/5/6/7 26.2.Flash Programming Commands ..................318 26.3. Debug Support.......................321 Rev. 1.2...
- Page 9 Figure 4.2. TQFP-100 Package Drawing................45 Figure 4.3. TQFP-64 Pinout Diagram..................46 Figure 4.4. TQFP-64 Package Drawing.................47 5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) ..............49 Figure 5.1. 12-Bit ADC0 Functional Block Diagram............49 Figure 5.2. Typical Temperature Sensor Transfer Function..........50 Figure 5.3. ADC0 Track and Conversion Example Timing ..........52 Figure 5.4.
- Page 10 Figure 8.5. DAC1H: DAC1 High Byte Register ..............103 Figure 8.6. DAC1L: DAC1 Low Byte Register ..............103 Figure 8.7. DAC1CN: DAC1 Control Register ..............104 9. VOLTAGE REFERENCE (C8051F120/2/4/6) ..............107 Figure 9.1. Voltage Reference Functional Block Diagram..........107 Figure 9.2. REF0CN: Reference Control Register ..............108 10.
- Page 11 C8051F120/1/2/3/4/5/6/7 Figure 10.1. Voltage Reference Functional Block Diagram ..........109 Figure 10.2. REF0CN: Reference Control Register ..............110 11. COMPARATORS........................111 Figure 11.1. Comparator Functional Block Diagram ............111 Figure 11.2. Comparator Hysteresis Plot................113 Figure 11.3. CPT0CN: Comparator0 Control Register ............114 Figure 11.4. CPT0MD: Comparator0 Mode Selection Register ...........115 Figure 11.5.
- Page 12 C8051F120/1/2/3/4/5/6/7 Figure 13.8. MAC0CF: MAC0 Configuration Register ............162 Figure 13.9. MAC0STA: MAC0 Status Register ..............163 Figure 13.10. MAC0AH: MAC0 A High Byte Register ............163 Figure 13.11. MAC0AL: MAC0 A Low Byte Register ............164 Figure 13.12. MAC0BH: MAC0 B High Byte Register............164 Figure 13.13.
- Page 13 C8051F120/1/2/3/4/5/6/7 Figure 18.1. EMI0CN: External Memory Interface Control ..........201 Figure 18.2. EMI0CF: External Memory Configuration ............201 Figure 18.3. Multiplexed Configuration Example..............202 Figure 18.4. Non-multiplexed Configuration Example ............203 Figure 18.5. EMIF Operating Modes..................204 Figure 18.6. EMI0TC: External Memory Timing Control ............206 Figure 18.7.
- Page 14 C8051F120/1/2/3/4/5/6/7 Figure 20.6. Typical Slave Transmitter Sequence ..............241 Figure 20.7. Typical Slave Receiver Sequence ..............241 Figure 20.8. SMB0CN: SMBus0 Control Register ...............243 Figure 20.9. SMB0CR: SMBus0 Clock Rate Register ............244 Figure 20.10. SMB0DAT: SMBus0 Data Register ...............245 Figure 20.11. SMB0ADR: SMBus0 Address Register............245 Figure 20.12.
- Page 15 C8051F120/1/2/3/4/5/6/7 24. TIMERS..........................285 Figure 24.1. T0 Mode 0 Block Diagram................286 Figure 24.2. T0 Mode 2 Block Diagram................287 Figure 24.3. T0 Mode 3 Block Diagram................288 Figure 24.4. TCON: Timer Control Register.................289 Figure 24.5. TMOD: Timer Mode Register................290 Figure 24.6. CKCON: Clock Control Register..............291 Figure 24.7.
- Page 16 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
- Page 17 2. ABSOLUTE MAXIMUM RATINGS .................36 Table 2.1. Absolute Maximum Ratings* ................36 3. GLOBAL DC ELECTRICAL CHARACTERISTICS .............37 Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3) ........37 Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) ........38 4. PINOUT AND PACKAGE DEFINITIONS ...............39 Table 4.1. Pin Definitions ......................39 5.
- Page 18 C8051F120/1/2/3/4/5/6/7 Table 19.1.Port I/O DC Electrical Characteristics ..............215 20. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) ..........237 Table 20.1.SMB0STA Status Codes and States ..............247 21. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........249 Table 21.1.SPI Slave Timing Parameters ................262 22. UART0 ..........................263 Table 22.1.UART0 Modes ....................264...
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Page 19: System Overview
Each MCU is specified for operation over the industrial temperature range (-45° C to +85° C). The Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F120/2/4/6 are available in a 100-pin TQFP pack- age (see block diagrams in Figure 1.1 and Figure 1.3). -
Page 20: Table 1.1. Product Selection Guide
C8051F120/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F120 100 128k 8448 2 100TQFP C8051F121 100 128k 8448 64TQFP C8051F122 100 128k 8448 2 100TQFP C8051F123 100 128k 8448 64TQFP C8051F124 128k 8448 2 100TQFP C8051F125 128k 8448 64TQFP C8051F126 128k 8448... -
Page 21: Figure 1.1. C8051F120/124 Block Diagram
C8051F120/1/2/3/4/5/6/7 Figure 1.1. C8051F120/124 Block Diagram Port I/O Config. Digital Power DGND UART0 P0.0 DGND DGND SFR Bus UART1 P0.7 SMBus Analog Power AGND P1.0/AIN2.0 SPI Bus AGND 256 byte P1.7/AIN2.7 Boundary Scan JTAG Logic Timers 0, Debug HW P2.0... -
Page 22: Figure 1.2. C8051F121/125 Block Diagram
C8051F120/1/2/3/4/5/6/7 Figure 1.2. C8051F121/125 Block Diagram Port I/O Config. Digital Power DGND UART0 P0.0 DGND DGND SFR Bus UART1 P0.7 SMBus Analog Power AGND P1.0/AIN2.0 SPI Bus 256 byte P1.7/AIN2.7 Boundary Scan JTAG Logic Timers 0, Debug HW P2.0 1, 2, 4... -
Page 23: Figure 1.3. C8051F122/126 Block Diagram
C8051F120/1/2/3/4/5/6/7 Figure 1.3. C8051F122/126 Block Diagram Port I/O Config. Digital Power DGND UART0 P0.0 DGND DGND SFR Bus UART1 P0.7 SMBus Analog Power AGND P1.0/AIN2.0 SPI Bus AGND 256 byte P1.7/AIN2.7 Boundary Scan JTAG Logic Timers 0, Debug HW P2.0... -
Page 24: Figure 1.4. C8051F123/127 Block Diagram
C8051F120/1/2/3/4/5/6/7 Figure 1.4. C8051F123/127 Block Diagram Port I/O Config. Digital Power DGND UART0 P0.0 DGND DGND SFR Bus UART1 P0.7 SMBus Analog Power AGND P1.0/AIN2.0 SPI Bus 256 byte P1.7/AIN2.7 Boundary Scan JTAG Logic Timers 0, Debug HW P2.0 1, 2, 4... -
Page 25: Microcontroller Core
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions With the CIP-51's maximum system clock at 100 MHz, the C8051F120/1/2/3 have a peak throughput of 100 MIPS (the C8051F124/5/6/7 have a peak throughput of 50 MIPS). Rev. 1.2... -
Page 26: Additional Features
C8051F120/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F12x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve over- all performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. -
Page 27: On-Chip Memory
C8051F120/1/2/3/4/5/6/7 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. -
Page 28: Jtag Debug And Boundary Scan
C8051F120/1/2/3/4/5/6/7 1.3. JTAG Debug and Boundary Scan The C8051F12x device family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG inter- face. -
Page 29: 16 X 16 Mac (Multiply And Accumulate) Engine
16 x 16 MAC (Multiply and Accumulate) Engine The C8051F120/1/2/3 devices include a multiply and accumulate engine which can be used to speed up many mathe- matical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or frac- tional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles. -
Page 30: Programmable Digital I/O And Crossbar
Programmable Digital I/O and Crossbar The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F120/2/4/6 have 4 additional ports (4, 5, 6, and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhance- ments. -
Page 31: Programmable Counter Array
C8051F120/1/2/3/4/5/6/7 1.6. Programmable Counter Array The C8051F12x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 6 pro- grammable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8. -
Page 32: Serial Ports
C8051F120/1/2/3/4/5/6/7 1.7. Serial Ports The C8051F12x MCU Family includes two Enhanced Full-Duplex UARTs, SPI Bus, and SMBus/I C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with any other. -
Page 33: 12-Bit Analog To Digital Converter
±1LSB. C8051F122/3/6/7 devices include a 10-bit SAR ADC with similar specifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output and an external VREF pin. On C8051F120/2/4/6 devices, ADC0 has its own dedicated VREF0 input pin; on C8051F121/3/5/7 devices, the ADC0 shares the VREFA input pin with the 8-bit ADC2. -
Page 34: 8-Bit Analog To Digital Converter
Special Function Registers. The ADC2 voltage reference is selected between the analog power supply (AV+) and an external VREF pin. On C8051F120/2/4/6 devices, ADC2 has its own dedicated VREF2 input pin; on C8051F121/3/5/7 devices, ADC2 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC2 into shutdown mode to save power. -
Page 35: Comparators And Dacs
DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F120/2/4/6 devices or via the internal voltage ref- erence on C8051F121/3/5/7 devices. -
Page 36: Absolute Maximum Ratings
C8051F120/1/2/3/4/5/6/7 ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings PARAMETER CONDITIONS UNITS Ambient temperature under bias °C Storage Temperature °C Voltage on any Pin (except VDD and Port I/O) with -0.3 VDD + respect to DGND Voltage on any Port I/O Pin or /RST with respect to -0.3... -
Page 37: Global Dc Electrical Characteristics
C8051F120/1/2/3/4/5/6/7 GLOBAL DC ELECTRICAL CHARACTERISTICS Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3) -40°C TO +85°C, 100 MHZ SYSTEM CLOCK UNLESS OTHERWISE SPECIFIED. PARAMETER CONDITIONS UNITS Analog Supply Voltage (Note 1) SYSCLK = 0 to 50 MHz SYSCLK > 50 MHz... -
Page 38: Table 3.2. Global Dc Electrical Characteristics (C8051F124/5/6/7)
C8051F120/1/2/3/4/5/6/7 Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) -40°C TO +85°C, 50 MHZ SYSTEM CLOCK UNLESS OTHERWISE SPECIFIED. PARAMETER CONDITIONS UNITS Analog Supply Voltage (Note 1) Analog Supply Current Internal REF, ADC, DAC, Compar- ators all active Analog Supply Current with Internal REF, ADC, DAC, Compar- µA... -
Page 39: Pinout And Package Definitions
C8051F120/1/2/3/4/5/6/7 PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions Pin Numbers Type Name F120/ F121/ Description 2/4/6 3/5/7 37, 64, 24, 41, Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. DGND 38, 63, 25, 40, Digital Ground. Must be tied to Ground. - Page 40 C8051F120/1/2/3/4/5/6/7 Table 4.1. Pin Definitions Pin Numbers Type Name F120/ F121/ Description 2/4/6 3/5/7 AIN0.0 A In ADC0 Input Channel 0 (See ADC0 Specification for complete description). AIN0.1 A In ADC0 Input Channel 1 (See ADC0 Specification for complete description).
- Page 41 C8051F120/1/2/3/4/5/6/7 Table 4.1. Pin Definitions Pin Numbers Type Name F120/ F121/ Description 2/4/6 3/5/7 /RD/P0.6 D I/O /RD Strobe for External Memory Address bus Port 0.6 See Port Input/Output section for complete description. /WR/P0.7 D I/O /WR Strobe for External Memory Address bus Port 0.7...
- Page 42 C8051F120/1/2/3/4/5/6/7 Table 4.1. Pin Definitions Pin Numbers Type Name F120/ F121/ Description 2/4/6 3/5/7 A15m/A7/P2.7 D I/O Port 2.7. See Port Input/Output section for complete description. AD0/D0/P3.0 D I/O Bit 0 External Memory Address/Data bus (Multiplexed mode) Bit 0 External Memory Data bus (Non-multiplexed mode) Port 3.0...
- Page 43 C8051F120/1/2/3/4/5/6/7 Table 4.1. Pin Definitions Pin Numbers Type Name F120/ F121/ Description 2/4/6 3/5/7 A12/P5.4 D I/O Port 5.4. See Port Input/Output section for complete description. A13/P5.5 D I/O Port 5.5. See Port Input/Output section for complete description. A14/P5.6 D I/O Port 5.6. See Port Input/Output section for complete description.
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Page 44: Figure 4.1. Tqfp-100 Pinout Diagram
C8051F120/1/2/3/4/5/6/7 Figure 4.1. TQFP-100 Pinout Diagram A13m/A5/P6.5 A14m/A6/P6.6 A15m/A7/P6.7 AD0/D0/P7.0 /RST AD1/D1/P7.1 CP1- AD2/D2/P7.2 CP1+ AD3/D3/P7.3 CP0- AD4/D4/P7.4 CP0+ AD5/D5/P7.5 AGND AD6/D6/P7.6 C8051F120 AD7/D7/P7.7 C8051F122 VREF AGND DGND C8051F124 P0.0 VREFD C8051F126 P0.1 VREF0 P0.2 VREF2 P0.3 AIN0.0 P0.4 AIN0.1 ALE/P0.5... -
Page 45: Figure 4.2. Tqfp-100 Package Drawing
C8051F120/1/2/3/4/5/6/7 Figure 4.2. TQFP-100 Package Drawing (mm) (mm) (mm) 1.20 0.05 0.15 0.95 1.00 1.05 0.17 0.22 0.27 16.00 14.00 0.50 16.00 14.00 PIN 1 DESIGNATOR Rev. 1.2... -
Page 46: Figure 4.3. Tqfp-64 Pinout Diagram
C8051F120/1/2/3/4/5/6/7 Figure 4.3. TQFP-64 Pinout Diagram CP1- /WR/P0.7 CP1+ AD0/D0/P3.0 CP0- AD1/D1/P3.1 CP0+ AD2/D2/P3.2 AGND AD3/D3/P3.3 AD4/D4/P3.4 C8051F121 VREF AD5/D5/P3.5 C8051F123 VREFA C8051F125 AIN0.0 DGND AIN0.1 AD6/D6/P3.6 C8051F127 AIN0.2 AD7/D7/P3.7 AIN0.3 A8m/A0/P2.0 AIN0.4 A9m/A1/P2.1 AIN0.5 A10m/A2/P2.2 AIN0.6 A11m/A3/P2.3 AIN0.7 A12m/A4/P2.4... -
Page 47: Figure 4.4. Tqfp-64 Package Drawing
C8051F120/1/2/3/4/5/6/7 Figure 4.4. TQFP-64 Package Drawing (mm) (mm) (mm) 1.20 0.05 0.15 0.95 1.05 0.17 0.22 0.27 12.00 10.00 PIN 1 DESIGNATOR 0.50 12.00 10.00 Rev. 1.2... - Page 48 C8051F120/1/2/3/4/5/6/7 Rev. 1.2...
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Page 49: Adc0 (12-Bit Adc, C8051F120/1/4/5 Only)
C8051F120/1/2/3/4/5/6/7 ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) The ADC0 subsystem for the C8051F120/1/4/5 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis- ters shown in Figure 5.1. -
Page 50: Figure 5.2. Typical Temperature Sensor Transfer Function
C8051F120/1/2/3/4/5/6/7 The Temperature Sensor transfer function is shown in Figure 5.2. The output voltage (V ) is the PGA input when TEMP the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. -
Page 51: Adc Modes Of Operation
C8051F120/1/2/3/4/5/6/7 5.2. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock divided by the value held in the ADCSC bits of register ADC0CF. 5.2.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conver- sion Mode bits (AD0CM1, AD0CM0) in ADC0CN. -
Page 52: Tracking Modes
C8051F120/1/2/3/4/5/6/7 5.2.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low- power track-and-hold mode. -
Page 53: Settling Time Requirements
C8051F120/1/2/3/4/5/6/7 5.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum track- ing time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. -
Page 54: Figure 5.5. Amx0Cf: Amux0 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 5.5. AMX0CF: AMUX0 Configuration Register SFR Page: 0xBA SFR Address: Reset Value AIN67IC AIN45IC AIN23IC AIN01IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit. -
Page 55: Figure 5.6. Amx0Sl: Amux0 Channel Select Register
C8051F120/1/2/3/4/5/6/7 Figure 5.6. AMX0SL: AMUX0 Channel Select Register SFR Page: 0xBB SFR Address: Reset Value AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bits3-0: AMX0AD3-0: AMX0 Address Bits. -
Page 56: Figure 5.7. Adc0Cf: Adc0 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 5.7. ADC0CF: ADC0 Configuration Register SFR Page: 0xBC SFR Address: Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. The SAR Conversion clock is derived from system clock by the following equation, where AD0SC... -
Page 57: Figure 5.8. Adc0Cn: Adc0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 5.8. ADC0CN: ADC0 Control Register SFR Page: 0xE8 (bit addressable) SFR Address: Reset Value AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. -
Page 58: Figure 5.9. Adc0H: Adc0 Data Word Msb Register
C8051F120/1/2/3/4/5/6/7 Figure 5.9. ADC0H: ADC0 Data Word MSB Register SFR Page: 0xBF SFR Address: Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits of the 12-bit ADC0 Data Word. -
Page 59: Figure 5.11. Adc0 Data Word Example
C8051F120/1/2/3/4/5/6/7 Figure 5.11. ADC0 Data Word Example 12-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0 (ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading, otherwise = 0000b). ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1 (ADC0L[3:0] = 0000b). -
Page 60: Adc0 Programmable Window Detector
C8051F120/1/2/3/4/5/6/7 5.3. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. -
Page 61: Figure 5.14. Adc0Lth: Adc0 Less-Than Data High Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register SFR Page: 0xC7 SFR Address: Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register... -
Page 62: Figure 5.16. 12-Bit Adc0 Window Interrupt Example: Right Justified Single-Ended Data
C8051F120/1/2/3/4/5/6/7 Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AGND) (AD0.0 - AGND) Word Word REF x (4095/4096) 0x0FFF REF x (4095/4096) 0x0FFF AD0WINT AD0WINT=1 not affected... -
Page 63: Figure 5.17. 12-Bit Adc0 Window Interrupt Example: Right Justified Differential Data
C8051F120/1/2/3/4/5/6/7 Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AD0.1) (AD0.0 - AD0.1) Word Word REF x (2047/2048) 0x07FF REF x (2047/2048) 0x07FF AD0WINT AD0WINT=1 not affected... -
Page 64: Figure 5.18. 12-Bit Adc0 Window Interrupt Example: Left Justified Single-Ended Data
C8051F120/1/2/3/4/5/6/7 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AGND) (AD0.0 - AGND) Word Word REF x (4095/4096) 0xFFF0 REF x (4095/4096) 0xFFF0 AD0WINT AD0WINT=1 not affected... -
Page 65: Figure 5.19. 12-Bit Adc0 Window Interrupt Example: Left Justified Differential Data
C8051F120/1/2/3/4/5/6/7 Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AD0.1) (AD0.0 - AD0.1) Word Word REF x (2047/2048) 0x7FF0 REF x (2047/2048) 0x7FF0 AD0WINT AD0WINT=1 not affected... -
Page 66: Table 5.1. 12-Bit Adc0 Electrical Characteristics (C8051F120/1/4/5)
C8051F120/1/2/3/4/5/6/7 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/5) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS UNITS DC ACCURACY Resolution bits Integral Nonlinearity ±1 Differential Nonlinearity Guaranteed Monotonic ±1... -
Page 67: Adc0 (10-Bit Adc, C8051F122/3/6/7 Only)
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis- ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in Section “9. VOLTAGE REFERENCE (C8051F120/2/4/6)” on page 107 for C8051F120/2/4/6 devices, or Section “10. VOLTAGE REF- ERENCE (C8051F121/3/5/7)”... -
Page 68: Figure 6.2. Typical Temperature Sensor Transfer Function
C8051F120/1/2/3/4/5/6/7 The Temperature Sensor transfer function is shown in Figure 6.2. The output voltage (V ) is the PGA input when TEMP the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. -
Page 69: Adc Modes Of Operation
C8051F120/1/2/3/4/5/6/7 6.2. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock divided by the value held in the ADCSC bits of register ADC0CF. 6.2.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conver- sion Mode bits (AD0CM1, AD0CM0) in ADC0CN. -
Page 70: Tracking Modes
C8051F120/1/2/3/4/5/6/7 6.2.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low- power track-and-hold mode. -
Page 71: Settling Time Requirements
C8051F120/1/2/3/4/5/6/7 6.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum track- ing time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. -
Page 72: Figure 6.5. Amx0Cf: Amux0 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 6.5. AMX0CF: AMUX0 Configuration Register SFR Page: 0xBA SFR Address: Reset Value AIN67IC AIN45IC AIN23IC AIN01IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit. -
Page 73: Figure 6.6. Amx0Sl: Amux0 Channel Select Register
C8051F120/1/2/3/4/5/6/7 Figure 6.6. AMX0SL: AMUX0 Channel Select Register SFR Page: 0xBB SFR Address: Reset Value AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bits3-0: AMX0AD3-0: AMX0 Address Bits. -
Page 74: Figure 6.7. Adc0Cf: Adc0 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 6.7. ADC0CF: ADC0 Configuration Register SFR Page: 0xBC SFR Address: Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers... -
Page 75: Figure 6.8. Adc0Cn: Adc0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 6.8. ADC0CN: ADC0 Control Register SFR Page: 0xE8 (bit addressable) SFR Address: Reset Value AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. -
Page 76: Figure 6.9. Adc0H: Adc0 Data Word Msb Register
C8051F120/1/2/3/4/5/6/7 Figure 6.9. ADC0H: ADC0 Data Word MSB Register SFR Page: 0xBF SFR Address: Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits of the 10-bit ADC0 Data Word. -
Page 77: Figure 6.11. Adc0 Data Word Example
C8051F120/1/2/3/4/5/6/7 Figure 6.11. ADC0 Data Word Example 10-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: ADC0H[1:0]:ADC0L[7:0], if AD0LJST = 0 (ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise = 000000b). ADC0H[7:0]:ADC0L[7:6], if AD0LJST = 1 (ADC0L[5:0] = 00b). -
Page 78: Adc0 Programmable Window Detector
C8051F120/1/2/3/4/5/6/7 6.3. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. -
Page 79: Figure 6.14. Adc0Lth: Adc0 Less-Than Data High Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register SFR Page: 0xC7 SFR Address: Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: High byte of ADC0 Less-Than Data Word. Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register... -
Page 80: Figure 6.16. 10-Bit Adc0 Window Interrupt Example: Right Justified Single-Ended Data
C8051F120/1/2/3/4/5/6/7 Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AGND) (AD0.0 - AGND) Word Word REF x (1023/1024) 0x03FF REF x (1023/1024) 0x03FF ADWINT ADWINT=1 not affected... -
Page 81: Figure 6.17. 10-Bit Adc0 Window Interrupt Example: Right Justified Differential Data
C8051F120/1/2/3/4/5/6/7 Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AD0.1) (AD0.0 - AD0.1) Word Word REF x (511/512) 0x01FF REF x (511/512) 0x01FF ADWINT ADWINT=1 not affected... -
Page 82: Figure 6.18. 10-Bit Adc0 Window Interrupt Example: Left Justified Single-Ended Data
C8051F120/1/2/3/4/5/6/7 Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AGND) (AD0.0 - AGND) Word Word REF x (1023/1024) 0xFFC0 REF x (1023/1024) 0xFFC0 ADWINT ADWINT=1 not affected... -
Page 83: Figure 6.19. 10-Bit Adc0 Window Interrupt Example: Left Justified Differential Data
C8051F120/1/2/3/4/5/6/7 Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage ADC Data Input Voltage ADC Data (AD0.0 - AD0.1) (AD0.0 - AD0.1) Word Word REF x (511/512) 0x7FC0 REF x (511/512) 0x7FC0 ADWINT ADWINT=1 not affected... -
Page 84: Table 6.1. 10-Bit Adc0 Electrical Characteristics (C8051F122/3/6/7)
C8051F120/1/2/3/4/5/6/7 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F122/3/6/7) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS UNITS DC ACCURACY Resolution bits Integral Nonlinearity ±1 Differential Nonlinearity Guaranteed Monotonic ±1... -
Page 85: Adc2 (8-Bit Adc)
C8051F120/1/2/3/4/5/6/7 ADC2 (8-BIT ADC) The ADC2 subsystem for the C8051F120/1/2/3/4/5/6/7 consists of an 8-channel, configurable analog multiplexer (AMUX2), a programmable gain amplifier (PGA2), and a 500 ksps, 8-bit successive-approximation-register ADC with integrated track-and-hold (see block diagram in Figure 7.1). The AMUX2, PGA2, and Data Conversion Modes are all configurable under software control via the Special Function Registers shown in Figure 7.1. -
Page 86: Adc2 Modes Of Operation
C8051F120/1/2/3/4/5/6/7 7.2. ADC2 Modes of Operation ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a divided version of the system clock, determined by the AD2SC bits in the ADC2CF register. The maximum ADC2 conversion clock is 7.5 MHz. -
Page 87: Figure 7.2. Adc2 Track And Conversion Example Timing
C8051F120/1/2/3/4/5/6/7 Figure 7.2. ADC2 Track and Conversion Example Timing A. ADC Timing for External Trigger Source CNVSTR2 (AD2CM[2:0]=010) SAR Clocks Low Power AD2TM=1 Track Convert Low Power Mode or Convert AD2TM=0 Track or Convert Convert Track B. ADC Timing for Internal Trigger Source... -
Page 88: Settling Time Requirements
C8051F120/1/2/3/4/5/6/7 7.2.3. Settling Time Requirements When the ADC2 input configuration is changed (i.e., a different MUX or PGA selection), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resis- tance, the ADC2 sampling capacitance, any external source resistance, and the accuracy required for the conversion. -
Page 89: Figure 7.4. Amx2Cf: Amux2 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 7.4. AMX2CF: AMUX2 Configuration Register SFR Page: 0xBA SFR Address: Reset Value PIN67IC PIN45IC PIN23IC PIN01IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: PIN67IC: AIN2.6, AIN2.7 Input Pair Configuration Bit. -
Page 90: Figure 7.5. Amx2Sl: Amux2 Channel Select Register
C8051F120/1/2/3/4/5/6/7 Figure 7.5. AMX2SL: AMUX2 Channel Select Register SFR Page: 0xBB SFR Address: Reset Value AMX2AD2 AMX2AD1 AMX2AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: UNUSED. Read = 00000b; Write = don’t care. Bits2-0: AMX2AD2-0: AMX2 Address Bits. -
Page 91: Figure 7.6. Adc2Cf: Adc2 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 7.6. ADC2CF: ADC2 Configuration Register SFR Page: 0xBC SFR Address: Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 AMP2GN1 AMP2GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD2SC refers... -
Page 92: Figure 7.7. Adc2Cn: Adc2 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 7.7. ADC2CN: ADC2 Control Register SFR Page: 0xE8 (bit addressable) SFR Address: Reset Value AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 AD2CM0 AD2WINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. -
Page 93: Figure 7.8. Adc2: Adc2 Data Word Register
C8051F120/1/2/3/4/5/6/7 Figure 7.8. ADC2: ADC2 Data Word Register SFR Page: 0xBE SFR Address: Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: ADC2 Data Word. Figure 7.9. ADC2 Data Word Example Single-Ended Example: 8-bit ADC Data Word appears in the ADC2 Data Word Register as follows: Example: ADC2 Data Word Conversion Map, Single-Ended AIN2.0 Input... -
Page 94: Adc2 Programmable Window Detector
C8051F120/1/2/3/4/5/6/7 7.3. ADC2 Programmable Window Detector The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD2WINT in register ADC2CN) can also be used in polled mode. -
Page 95: Window Detector In Differential Mode
C8051F120/1/2/3/4/5/6/7 7.3.2. Window Detector In Differential Mode Figure 7.11 shows two example window comparisons for differential mode, with ADC2LT = 0x10 (+16d) and ADC2GT = 0xFF (-1d). Notice that in Differential mode, the codes vary from -VREF to VREF*(127/128) and are represented as 8-bit 2’s complement signed integers. -
Page 96: Figure 7.12. Adc2Gt: Adc2 Greater-Than Data Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 7.12. ADC2GT: ADC2 Greater-Than Data Byte Register SFR Page: 0xC4 SFR Address: Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-0: ADC2 Greater-Than Data Word. Figure 7.13. ADC2LT: ADC2 Less-Than Data Byte Register SFR Page:... -
Page 97: Table 7.1. Adc2 Electrical Characteristics
C8051F120/1/2/3/4/5/6/7 Table 7.1. ADC2 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF2 = 2.40 V (REFBE=0), PGA gain = 1, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS UNITS DC ACCURACY Resolution bits Integral Nonlinearity ±1 Differential Nonlinearity Guaranteed Monotonic ±1... - Page 98 C8051F120/1/2/3/4/5/6/7 Rev. 1.2...
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Page 99: Dacs, 12-Bit Voltage Mode
DAC output is maintained in a high-impedance state, and the DAC supply current falls to 1 µA or less. The volt- age reference for each DAC is supplied at the VREFD pin (C8051F120/2/4/6 devices) or the VREF pin (C8051F121/ 3/5/7 devices). -
Page 100: Update Output Based On Timer Overflow
C8051F120/1/2/3/4/5/6/7 a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the desired value (typ- ically 0x00), and writing data to only DAC0H (also see Section 8.2... -
Page 101: Figure 8.2. Dac0H: Dac0 High Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 8.2. DAC0H: DAC0 High Byte Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD3 SFR Page: Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register Reset Value... -
Page 102: Figure 8.4. Dac0Cn: Dac0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 8.4. DAC0CN: DAC0 Control Register Reset Value DAC0EN DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 SFR Page: Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. -
Page 103: Figure 8.5. Dac1H: Dac1 High Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 8.5. DAC1H: DAC1 High Byte Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD3 SFR Page: Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register Reset Value... -
Page 104: Figure 8.7. Dac1Cn: Dac1 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 8.7. DAC1CN: DAC1 Control Register Reset Value DAC1EN DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 SFR Page: Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. -
Page 105: Table 8.1. Dac Electrical Characteristics
C8051F120/1/2/3/4/5/6/7 Table 8.1. DAC Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified PARAMETER CONDITIONS UNITS STATIC PERFORMANCE Resolution bits Integral Nonlinearity ±1.5 Differential Nonlinearity ±1... - Page 106 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
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Page 107: Voltage Reference (C8051F120/2/4/6)
C8051F120/1/2/3/4/5/6/7 VOLTAGE REFERENCE (C8051F120/2/4/6) The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage refer- ence output. -
Page 108: Figure 9.2. Ref0Cn: Reference Control Register
The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 49 for C8051F120/1/4/5 devices, or Section “6.1. Analog Multiplexer and PGA” on page 67 for C8051F122/3/6/7 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. -
Page 109: Voltage Reference (C8051F121/3/5/7)
C8051F120/1/2/3/4/5/6/7 VOLTAGE REFERENCE (C8051F121/3/5/7) The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components or to the VREFA input pin shown in Figure 10.1. -
Page 110: Figure 10.2. Ref0Cn: Reference Control Register
The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 49 for C8051F120/1/4/5 devices, or Section “6.1. Analog Multiplexer and PGA” on page 67 for C8051F122/3/6/7 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. -
Page 111: Comparators
C8051F120/1/2/3/4/5/6/7 COMPARATORS C8051F120/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators as shown in Figure 11.1. The inputs of each Comparator are available at dedicated pins. The output of each comparator is optionally available at the package pins via the I/O crossbar. When assigned to package pins, each comparator output can be programmed to operate in open drain or push-pull modes. - Page 112 C8051F120/1/2/3/4/5/6/7 Comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (For interrupt enable and priority control, see Section “12.7. Interrupt Handler” on page 146). The CP0FIF flag is set upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software.
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Page 113: Figure 11.2. Comparator Hysteresis Plot
C8051F120/1/2/3/4/5/6/7 Figure 11.2. Comparator Hysteresis Plot CP0+ VIN+ CP0- VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ OUTPUT Negative Hysteresis Maximum Disabled Negative Hysteresis Positive Hysteresis Maximum Disabled Positive Hysteresis Rev. -
Page 114: Figure 11.3. Cpt0Cn: Comparator0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 11.3. CPT0CN: Comparator0 Control Register SFR Page: 0x88 SFR Address: Reset Value CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. -
Page 115: Figure 11.4. Cpt0Md: Comparator0 Mode Selection Register
C8051F120/1/2/3/4/5/6/7 Figure 11.4. CPT0MD: Comparator0 Mode Selection Register SFR Page: 0x89 SFR Address: Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP0RIE: Comparator 0 Rising-Edge Interrupt Enable Bit. -
Page 116: Figure 11.5. Cpt1Cn: Comparator1 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 11.5. CPT1CN: Comparator1 Control Register SFR Page: 0x88 SFR Address: Reset Value CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. -
Page 117: Figure 11.6. Cpt1Md: Comparator1 Mode Selection Register
C8051F120/1/2/3/4/5/6/7 Figure 11.6. CPT1MD: Comparator1 Mode Selection Register SFR Page: 0x89 SFR Address: Reset Value CP1RIE CP1FIE CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP1RIE: Comparator 1 Rising-Edge Interrupt Enable Bit. -
Page 118: Table 11.1.Comparator Electrical Characteristics
C8051F120/1/2/3/4/5/6/7 Table 11.1. Comparator Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS UNITS CPn+ - CPn- = 100 mV Response Time: † Mode 0, Vcm = 1.5 V CPn+ - CPn- = -100 mV... -
Page 119: Microcontroller
C8051F120/1/2/3/4/5/6/7 CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see descrip-... -
Page 120: Instruction Set
C8051F120/1/2/3/4/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe- cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc- tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. -
Page 121: Table 12.1.Cip-51 Instruction Set Summary
C8051F120/1/2/3/4/5/6/7 MEMORY” on page 185). The External Memory Interface provides a fast access to off-chip XRAM (or memory- mapped peripherals) via the MOVX instruction. Refer to Section “18. EXTERNAL DATA MEMORY INTER- FACE AND ON-CHIP XRAM” on page 199 for details. - Page 122 C8051F120/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary Clock Mnemonic Description Bytes Cycles XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive-OR A to direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A...
- Page 123 C8051F120/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary Clock Mnemonic Description Bytes Cycles CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry...
- Page 124 C8051F120/1/2/3/4/5/6/7 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps.
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Page 125: Memory Organization
C8051F120/1/2/3/4/5/6/7 12.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa- rate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. -
Page 126: Figure 12.3. Psbank: Program Space Bank Select Register
C8051F120/1/2/3/4/5/6/7 Figure 12.3. PSBANK: Program Space Bank Select Register Reset Value COBANK IFBANK 00010001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 SFR Page: All Pages Bits 7-6: Reserved. Bits 5-4: COBANK: Constant Operations Bank Select. These bits select which FLASH bank is targeted during constant operations (MOVC and FLASH MOVX) involving addresses 0x8000 to 0xFFFF. -
Page 127: Data Memory
C8051F120/1/2/3/4/5/6/7 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. -
Page 128: Special Function Registers
C8051F120/1/2/3/4/5/6/7 12.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFR’s). The SFR’s provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFR’s found in a typical 8051 implementation as well as implementing additional SFR’s used to configure and access the sub-systems unique to the MCU. - Page 129 C8051F120/1/2/3/4/5/6/7 Figure 12.5. SFR Page Stack SFRPGCN Bit Interrupt Logic SFRPAGE CIP-51 SFRNEXT SFRLAST Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). This function defaults to ‘enabled’...
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Page 130: 3.Sfr Page Stack Example
C8051F120/1/2/3/4/5/6/7 12.2.6.3. SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is exe- cuting in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR Page 0x0F). -
Page 131: Figure 12.7. Sfr Page Stack After Adc2 Window Comparator Interrupt Occurs
C8051F120/1/2/3/4/5/6/7 While CIP-51 executes in-line code (writing values to Port 5 in this example), ADC2 Window Comparator Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to access ADC2’s SFR’s is then automatically placed in the SFRPAGE register (SFR Page 0x02). -
Page 132: Figure 12.8. Sfr Page Stack Upon Pca Interrupt Occurring During An Adc2 Isr
C8051F120/1/2/3/4/5/6/7 While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high prior- ity PCA ISR. -
Page 133: Figure 12.9. Sfr Page Stack Upon Return From Pca Interrupt
C8051F120/1/2/3/4/5/6/7 On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC2 ISR can continue to access SFR’s as it did prior to the PCA interrupt. -
Page 134: Figure 12.10. Sfr Page Stack Upon Return From Adc2 Window Interrupt
C8051F120/1/2/3/4/5/6/7 On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as it did prior to the interrupts occurring. -
Page 135: Figure 12.11. Sfrpgcn: Sfr Page Control Register
C8051F120/1/2/3/4/5/6/7 Figure 12.11. SFRPGCN: SFR Page Control Register Reset Value SFRPGEN 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x96 SFR Page: Bits7-1: Reserved. Bit0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and automati- cally switch the SFR page to the corresponding peripheral or function’s SFR page. -
Page 136: Figure 12.13. Sfrnext: Sfr Next Register
C8051F120/1/2/3/4/5/6/7 Figure 12.13. SFRNEXT: SFR Next Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x85 SFR Page: All Pages Bits7-0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third entry. -
Page 137: Table 12.2.Special Function Register (Sfr) Memory Map
C8051F120/1/2/3/4/5/6/7 Table 12.2. Special Function Register (SFR) Memory Map 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F) SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL1 PCA0CPH1 WDTCN (ALL PAGES) EIP1 EIP2 (ALL (ALL (ALL PAGES) PAGES) PAGES) ADC0CN PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3... -
Page 138: Table 12.3.Special Function Registers
C8051F120/1/2/3/4/5/6/7 Table 12.2. Special Function Register (SFR) Memory Map FLSCL PSBANK (ALL (ALL PAGES) PAGES) FLACL SADDR0 (ALL PAGES) P1MDIN EMI0TC EMI0CN EMI0CF (ALL PAGES) CCH0CN CCH0TN CCH0LC P0MDOUT P1MDOUT P2MDOUT P3MDOUT SCON0 SBUF0 SPI0CFG SPI0DAT SPI0CKR SCON1 SBUF1 CCH0MA... - Page 139 C8051F120/1/2/3/4/5/6/7 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description Page No. Page ADC0H 0xBF ADC0 Data Word High Byte page 58*, page 76** ADC0L 0xBE ADC0 Data Word Low Byte...
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Page 140: Figure 12.5. Sfr
C8051F120/1/2/3/4/5/6/7 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description Page No. Page MAC0ACC0 0x93 MAC0 Accumulator Byte 0 (LSB) page 165 MAC0ACC1 0x94 MAC0 Accumulator Byte 1 page 165... - Page 141 C8051F120/1/2/3/4/5/6/7 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description Page No. Page PCA0CPL4 0xED PCA Module 4 Capture/Compare Low Byte page 314 PCA0CPL5 0xE1 PCA Module 5 Capture/Compare Low Byte...
- Page 142 0xE3 Port I/O Crossbar Control 2 page 226 * Refers to a register in the C8051F120/1/4/5 only. ** Refers to a register in the C8051F122/3/6/7 only. † Refers to a register in the C8051F120/2/4/6 only. †† Refers to a register in the C8051F121/3/5/7 only.
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Page 143: Register Descriptions
C8051F120/1/2/3/4/5/6/7 12.6.4. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. -
Page 144: Figure 12.18. Psw: Program Status Word
C8051F120/1/2/3/4/5/6/7 Figure 12.18. PSW: Program Status Word Reset Value PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xD0 SFR Page: All Pages Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtrac- tion). -
Page 145: Figure 12.19. Acc: Accumulator
C8051F120/1/2/3/4/5/6/7 Figure 12.19. ACC: Accumulator Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xE0 SFR Page: All Pages Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. -
Page 146: Interrupt Handler
C8051F120/1/2/3/4/5/6/7 12.7. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the spe- cific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. -
Page 147: Table 12.4.Interrupt Summary
C8051F120/1/2/3/4/5/6/7 Table 12.4. Interrupt Summary Interrupt Priority Enable Priority Interrupt Source Pending Flags Vector Order Flag Control Always Always Reset 0x0000 None N/A N/A Enabled Highest External Interrupt 0 (/INT0) 0x0003 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 0x000B TF0 (TCON.5) -
Page 148: Interrupt Priorities
C8051F120/1/2/3/4/5/6/7 12.7.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter- rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. -
Page 149: Interrupt Register Descriptions
C8051F120/1/2/3/4/5/6/7 12.7.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). -
Page 150: Figure 12.22. Ip: Interrupt Priority
C8051F120/1/2/3/4/5/6/7 Figure 12.22. IP: Interrupt Priority Reset Value 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xB8 SFR Page: All Pages Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. -
Page 151: Figure 12.23. Eie1: Extended Interrupt Enable 1
C8051F120/1/2/3/4/5/6/7 Figure 12.23. EIE1: Extended Interrupt Enable 1 Reset Value ECP1R ECP1F ECP0R ECP0F EPCA0 EWADC0 ESMB0 ESPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 SFR Page: All Pages Bit7: ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt. -
Page 152: Figure 12.24. Eie2: Extended Interrupt Enable 2
C8051F120/1/2/3/4/5/6/7 Figure 12.24. EIE2: Extended Interrupt Enable 2 Reset Value EADC2 EWADC2 EADC0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE7 SFR Page: All Pages Bit7: UNUSED. Read = 0b, Write = don't care. Bit6: ES1: Enable UART1 Interrupt. -
Page 153: Figure 12.25. Eip1: Extended Interrupt Priority 1
C8051F120/1/2/3/4/5/6/7 Figure 12.25. EIP1: Extended Interrupt Priority 1 Reset Value PCP1R PCP1F PCP0R PCP0F PPCA0 PWADC0 PSMB0 PSPI0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 SFR Page: All Pages Bit7: PCP1R: Comparator1 (CP1) Rising Interrupt Priority Control. -
Page 154: Figure 12.26. Eip2: Extended Interrupt Priority 2
C8051F120/1/2/3/4/5/6/7 Figure 12.26. EIP2: Extended Interrupt Priority 2 Reset Value PADC2 PWADC2 PADC0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF7 SFR Page: All Pages Bit7: UNUSED. Read = 0b, Write = don't care. Bit6: ES1: UART1 Interrupt Priority Control. -
Page 155: Power Management Modes
C8051F120/1/2/3/4/5/6/7 12.8. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. -
Page 156: Figure 12.27. Pcon: Power Control
C8051F120/1/2/3/4/5/6/7 Figure 12.27. PCON: Power Control Reset Value STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x87 SFR Page: All Pages Bits7-3: Reserved. Bit1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. -
Page 157: Multiply And Accumulate (Mac0)
MULTIPLY AND ACCUMULATE (MAC0) The C8051F120/1/2/3 devices include a multiply and accumulate engine which can be used to speed up many mathe- matical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or frac- tional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles. -
Page 158: Integer And Fractional Math
C8051F120/1/2/3/4/5/6/7 13.2. Integer and Fractional Math MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed frac- tional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as 16-bit, 2’s comple- ment, integer values. -
Page 159: Operating In Multiply And Accumulate Mode
C8051F120/1/2/3/4/5/6/7 13.3. Operating in Multiply and Accumulate Mode MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to ‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A and MAC0B registers, and adds the result to the contents of the 40-bit MAC0 accumulator. -
Page 160: Rounding And Saturation
C8051F120/1/2/3/4/5/6/7 13.6. Rounding and Saturation A Rounding Engine is included, which can be used to provide a rounded result when operating on fractional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31-16 of the accumulator, as shown in Table 13.1. -
Page 161: Figure 13.6. Multiply Only Example
C8051F120/1/2/3/4/5/6/7 Figure 13.6. Multiply Only Example The example below implements the equation: × 4660 – – 1360720 MAC0CF, #01h ; Use integer numbers, and multiply only mode (add to zero) MAC0AH, #12h ; Load MAC0A register with 1234 hex = 4660 decimal... -
Page 162: Figure 13.8. Mac0Cf: Mac0 Configuration Register
C8051F120/1/2/3/4/5/6/7 Figure 13.8. MAC0CF: MAC0 Configuration Register Reset Value MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC3 SFR Page: 3 Bits 7-6: UNUSED: Read = 00b, Write = don’t care. -
Page 163: Figure 13.9. Mac0Sta: Mac0 Status Register
C8051F120/1/2/3/4/5/6/7 Figure 13.9. MAC0STA: MAC0 Status Register Reset Value MAC0HO MAC0Z MAC0SO MAC0N 00000100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xC0 SFR Page: 3 Bits 7-4: UNUSED: Read = 0000b, Write = don’t care. Bit 3: MAC0HO: Hard Overflow Flag. -
Page 164: Figure 13.11. Mac0Al: Mac0 A Low Byte Register
C8051F120/1/2/3/4/5/6/7 Figure 13.11. MAC0AL: MAC0 A Low Byte Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC1 SFR Page: 3 Bits 7-0: Low Byte (bits 7-0) of MAC0 A Register. Figure 13.12. MAC0BH: MAC0 B High Byte Register... -
Page 165: Figure 13.15. Mac0Acc2: Mac0 Accumulator Byte 2 Register
C8051F120/1/2/3/4/5/6/7 Figure 13.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x95 SFR Page: 3 Bits 7-0: Byte 2 (bits 23-16) of MAC0 Accumulator. Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages. -
Page 166: Figure 13.19. Mac0Rndh: Mac0 Rounding Register High Byte
C8051F120/1/2/3/4/5/6/7 Figure 13.19. MAC0RNDH: MAC0 Rounding Register High Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCF SFR Page: 3 Bits 7-0: High Byte (bits 15-8) of MAC0 Rounding Register. Figure 13.20. MAC0RNDL: MAC0 Rounding Register Low Byte... -
Page 167: Reset Sources
C8051F120/1/2/3/4/5/6/7 RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution. • Special Function Registers (SFRs) are initialized to their defined reset values. -
Page 168: Power-On Reset
C8051F120/1/2/3/4/5/6/7 14.1. Power-on Reset The C8051F120/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V level during power-up. See Figure 14.2 for timing diagram, and refer to Table 14.1 for the Electrical Characteristics of the power supply monitor circuit. -
Page 169: Missing Clock Detector Reset
C8051F120/1/2/3/4/5/6/7 14.4. Missing Clock Detector Reset The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the system clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source;... -
Page 170: Disable Wdt
C8051F120/1/2/3/4/5/6/7 14.7.2. Disable WDT Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates disabling the WDT: ; disable all interrupts WDTCN,#0DEh ; disable software watchdog timer WDTCN,#0ADh SETB ; re-enable interrupts The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored. -
Page 171: Figure 14.4. Rstsrc: Reset Source Register
C8051F120/1/2/3/4/5/6/7 Figure 14.4. RSTSRC: Reset Source Register Reset Value CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xEF SFR Page: Bit7: Reserved. Bit6: CNVRSEF: Convert Start 0 Reset Source Enable and Flag Write: 0: CNVSTR0 is not a reset source. -
Page 172: Table 14.1.Reset Electrical Characteristics
C8051F120/1/2/3/4/5/6/7 Table 14.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS UNITS = 8.5 mA, VDD = 2.7 V to 3.6 V /RST Output Low Voltage 0.7 x /RST Input High Voltage 0.3 x /RST Input Low Voltage /RST Input Leakage Current /RST = 0.0 V... -
Page 173: Oscillators
C8051F120/1/2/3/4/5/6/7 OSCILLATORS C8051F120/1/2/3/4/5/6/7 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled, disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 15.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or the on-chip phase-locked loop (PLL). -
Page 174: Figure 15.2. Oscicl: Internal Oscillator Calibration Register
C8051F120/1/2/3/4/5/6/7 Figure 15.2. OSCICL: Internal Oscillator Calibration Register Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8B SFR Page: Bits 7-0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. -
Page 175: External Oscillator Drive Circuit
C8051F120/1/2/3/4/5/6/7 Figure 15.4. CLKSEL: System Clock Selection Register Reset Value CLKDIV1 CLKDIV0 CLKSL1 CLKSL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x97 SFR Page: Bits 7-6: Reserved. Bits 5-4: CLKDIV1-0: Output SYSCLK Divide Factor. These bits can be used to pre-divide SYSCLK before it is output to a port pin through the crossbar. -
Page 176: Figure 15.5. Oscxcn: External Oscillator Control Register
C8051F120/1/2/3/4/5/6/7 Figure 15.5. OSCXCN: External Oscillator Control Register Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8C SFR Page: Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. -
Page 177: External Crystal Example
C8051F120/1/2/3/4/5/6/7 15.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 15.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 15.5 (OSCXCN register). -
Page 178: Phase-Locked Loop (Pll)
C8051F120/1/2/3/4/5/6/7 15.7. Phase-Locked Loop (PLL) The C8051F12x Family include a Phase-Locked-Loop (PLL), which is used to multiply the internal oscillator or an external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an out- put frequency between 25 MHz and 100 MHz, from a divided reference frequency between 5 MHz and 30 MHz. -
Page 179: Powering On And Initializing The Pll
C8051F120/1/2/3/4/5/6/7 15.7.3. Powering on and Initializing the PLL To set up and use the PLL as the system clock after power-up of the device, the following procedure should be imple- mented: Step 1. Ensure that the reference clock to be used (internal or external) is running and stable. -
Page 180: Figure 15.7. Pll0Cn: Pll Control Register
C8051F120/1/2/3/4/5/6/7 Figure 15.7. PLL0CN: PLL Control Register Reset Value PLLLCK PLLSRC PLLEN PLLPWR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x89 SFR Page: Bits 7-5: UNUSED: Read = 000b; Write = don’t care. Bit 4: PLLCK: PLL Lock Flag. -
Page 181: Figure 15.9. Pll0Mul: Pll Clock Scaler Register
C8051F120/1/2/3/4/5/6/7 Figure 15.9. PLL0MUL: PLL Clock Scaler Register Reset Value PLLN7 PLLN6 PLLN5 PLLN4 PLLN3 PLLN2 PLLN1 PLLN0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8E SFR Page: Bits 7-0: PLLN7-0: PLL Multiplier. These bits select the multiplication factor of the divided PLL reference clock. When set to any non- zero value, the multiplication factor will be equal to the value in PLLN7-0. -
Page 182: Table 15.2.Pll Frequency Characteristics
C8051F120/1/2/3/4/5/6/7 Table 15.2. PLL Frequency Characteristics -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS UNITS Input Frequency (Divided Reference Frequency) PLL Output Frequency (C8051F120/1/2/3) PLL Output Frequency (C8051F124/5/6/7) Table 15.3. PLL Lock Timing Characteristics -40°C to +85°C unless otherwise specified... - Page 183 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
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Page 185: Flash Memory
C8051F120/1/2/3/4/5/6/7 FLASH MEMORY The C8051F12x family includes 128k + 256 bytes of on-chip, reprogrammable FLASH memory for program code and non-volatile data storage. The FLASH memory can be programmed in-system through the JTAG interface, or by software using the MOVX write instructions. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. -
Page 186: Erasing Flash Pages From Software
C8051F120/1/2/3/4/5/6/7 a single byte of a multi-byte data set, the data must be moved to temporary storage. The 128-byte sector-size facili- tates updating data without wasting program memory or RAM space. The 128-byte sectors are double-mapped over the 128k byte FLASH memory for MOVC reads and MOVX writes only; their addresses range from 0x00 to 0x7F and from 0x80 to 0xFF (see Figure 16.2). -
Page 187: Writing Flash Memory From Software
C8051F120/1/2/3/4/5/6/7 16.1.3. Writing FLASH Memory From Software Bytes in FLASH memory can be written one byte at a time, or in small blocks. The CHBLKW bit in register CCH0CN (Figure 17.4) controls whether a single byte or a block of bytes is written to FLASH during a write opera- tion. -
Page 188: Security Options
C8051F120/1/2/3/4/5/6/7 Write/Erase timing is automatically controlled by hardware. Note that 1024 bytes beginning at location 0x1FC00 are reserved. FLASH writes and erases targeting the reserved area should be avoided. Table 16.1. FLASH Electrical Characteristics VDD = 2.7 to 3.6 V; -40°C to +85°C... -
Page 189: Figure 16.2. Flash Program Memory Map And Security Bytes
C8051F120/1/2/3/4/5/6/7 Figure 16.2. FLASH Program Memory Map and Security Bytes Read and Write/Erase Security Bits. SFLE = 0 SFLE = 1 (Bit 7 is MSB.) 0x00FF 0x1FFFF Memory Block Scratchpad Memory Reserved (Data only) 0x1C000 - 0x1FBFD 0x0000 0x1FC00 0x18000 - 0x1BFFF... -
Page 190: Figure 16.3. Flacl: Flash Access Limit
The FLASH Access Limit security feature (see Figure 16.2) protects proprietary program code and data from being read by software running on the C8051F120/1/2/3/4/5/6/7. This feature provides support for OEMs that wish to pro- gram the MCU with proprietary value-added firmware before distribution. The value-added firmware can be pro- tected while allowing additional code to be programmed in remaining program memory space later. -
Page 191: Figure 16.4. Flscl: Flash Memory Control
C8051F120/1/2/3/4/5/6/7 Figure 16.4. FLSCL: FLASH Memory Control Reset Value FLRT Reserved Reserved Reserved FLWE 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: 0xB7 SFR Page: Bits 7-6: Unused. Bits 5-4: FLRT: FLASH Read Time. These bits should be programmed to the smallest allowed value, according to the system clock speed. -
Page 192: Figure 16.5. Psctl: Program Store Read/Write Control
C8051F120/1/2/3/4/5/6/7 Figure 16.5. PSCTL: Program Store Read/Write Control Reset Value SFLE PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: SFR Address: 0x8F SFR Page: Bits 7-3: UNUSED. Read = 00000b, Write = don't care. Bit 2:... -
Page 193: Branch Target Cache
The C8051F12x family of devices incorporate a 63x4 byte branch target cache with a 4-byte prefetch engine. Because the access time of the FLASH memory is 40ns, and the minimum instruction time is 10ns (C8051F120/1/2/ 3) or 20ns (C8051F124/5/6/7), the branch target cache and prefetch engine are necessary for full-speed code execu- tion. -
Page 194: Cache And Prefetch Optimization
C8051F120/1/2/3/4/5/6/7 beginning. When CHALGM is set to ‘1’, the cache will use the pseudo-random algorithm to replace cache locations. The pseudo-random algorithm uses a pseudo-random number to determine which cache location to replace. The cache can be manually emptied by writing a ‘1’ to the CHFLUSH bit (CCH0CN.4). -
Page 195: Figure 17.3. Cache Lock Operation
C8051F120/1/2/3/4/5/6/7 likely to be interrupted repeatedly (such as a code loop that is waiting for an interrupt to happen). Instructions that are part of an interrupt service routine (ISR) can also be excluded from caching. By default, ISR instructions are cached, but this can be disabled by clearing the CHISR bit (CCH0CN.2) to ‘0’. -
Page 196: Figure 17.4. Cch0Cn: Cache Control Register
C8051F120/1/2/3/4/5/6/7 Figure 17.4. CCH0CN: Cache Control Register Reset Value CHWREN CHRDEN CHPFEN CHFLSH CHRETI CHISR CHMOVC CHBLKW 11100110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA1 SFR Page: Bit 7: CHWREN: Cache Write Enable. This bit enables the processor to write to the cache memory. -
Page 197: Figure 17.5. Cch0Tn: Cache Tuning Register
C8051F120/1/2/3/4/5/6/7 Figure 17.5. CCH0TN: Cache Tuning Register Reset Value CHMSCTL CHALGM CHFIXM CHMSTH 00000100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 SFR Page: Bits 7-4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4-1). These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first be latched by reading the CHMSCTH bits in the CCH0MA Register (See Figure 17.7). -
Page 198: Figure 17.7. Cch0Ma: Cache Miss Accumulator
C8051F120/1/2/3/4/5/6/7 Figure 17.7. CCH0MA: Cache Miss Accumulator Reset Value CHMSOV CHMSCTH 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A SFR Page: Bit 7: CHMSOV: Cache Miss Penalty Overflow. This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was last written. -
Page 199: External Data Memory Interface And On-Chip Xram
C8051F120/1/2/3/4/5/6/7 EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM The C8051F12x MCUs include 8k bytes of on-chip RAM mapped into the external data memory space (XRAM), as well as an External Data Memory Interface which can be used to access off-chip memories and memory-mapped devices connected to the GPIO ports. -
Page 200: Port Selection And Configuration
18.3. Port Selection and Configuration The External Memory Interface can appear on Ports 3, 2, 1, and 0 (C8051F120/1/2/3/4/5/6/7 devices) or on Ports 7, 6, 5, and 4 (C8051F120/2/4/6 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are selected, the EMIFLE bit (XBR2.1) must be set to a ‘1’... -
Page 201: Figure 18.1. Emi0Cn: External Memory Interface Control
C8051F120/1/2/3/4/5/6/7 Figure 18.1. EMI0CN: External Memory Interface Control Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 SFR Page: Bits7-0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. -
Page 202: Multiplexed And Non-Multiplexed Selection
C8051F120/1/2/3/4/5/6/7 18.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 18.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. -
Page 203: Non-Multiplexed Configuration
C8051F120/1/2/3/4/5/6/7 18.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 18.4. See Section “18.6.1. Non-multiplexed Mode” on page 207 for more infor- mation about Non-multiplexed operation. -
Page 204: Memory Mode Selection
C8051F120/1/2/3/4/5/6/7 18.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 18.5, based on the EMIF Mode bits in the EMI0CF register (Figure 18.2). These modes are summarized below. More information about the different modes can be found in Section “18.6. -
Page 205: Split Mode With Bank Select
C8051F120/1/2/3/4/5/6/7 18.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the 8k boundary will access on-chip XRAM space. •... -
Page 206: Timing
C8051F120/1/2/3/4/5/6/7 18.6. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in Figure 18.6, and EMI0CF[1:0]. -
Page 207: Non-Multiplexed Mode
C8051F120/1/2/3/4/5/6/7 18.6.1. Non-multiplexed Mode 18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Figure 18.7. Non-multiplexed 16-bit MOVX Timing Nonmuxed 16-bit WRITE ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from DPH P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from DPL P2/P6... -
Page 208: 8-Bit Movx Without Bank Select: Emi0Cf[4:2] = '101' Or '111
C8051F120/1/2/3/4/5/6/7 18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 18.8. Non-multiplexed 8-bit MOVX without Bank Select Timing Nonmuxed 8-bit WRITE without Bank Select ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from R0 or R1 P2/P6... -
Page 209: 8-Bit Movx With Bank Select: Emi0Cf[4:2] = '110
C8051F120/1/2/3/4/5/6/7 18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Figure 18.9. Non-multiplexed 8-bit MOVX with Bank Select Timing Nonmuxed 8-bit WRITE with Bank Select ADDR[15:8] P1/P5 EMIF ADDRESS (8 MSBs) from EMI0CN P1/P5 ADDR[7:0] P2/P6 EMIF ADDRESS (8 LSBs) from R0 or R1... -
Page 210: Multiplexed Mode
C8051F120/1/2/3/4/5/6/7 18.6.2. Multiplexed Mode 18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Figure 18.10. Multiplexed 16-bit MOVX Timing Muxed 16-bit WRITE ADDR[15:8] P2/P6 EMIF ADDRESS (8 MSBs) from DPH P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 EMIF WRITE DATA... -
Page 211: 8-Bit Movx Without Bank Select: Emi0Cf[4:2] = '001' Or '011
C8051F120/1/2/3/4/5/6/7 18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Figure 18.11. Multiplexed 8-bit MOVX without Bank Select Timing Muxed 8-bit WRITE Without Bank Select ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 EMIF WRITE DATA P3/P7... -
Page 212: 8-Bit Movx With Bank Select: Emi0Cf[4:2] = '010
C8051F120/1/2/3/4/5/6/7 18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Figure 18.12. Multiplexed 8-bit MOVX with Bank Select Timing Muxed 8-bit WRITE with Bank Select ADDR[15:8] P2/P6 EMIF ADDRESS (8 MSBs) from EMI0CN P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0]... -
Page 213: Table 18.1.Ac Parameters For External Memory Interface
C8051F120/1/2/3/4/5/6/7 Table 18.1. AC Parameters for External Memory Interface † PARAMETER DESCRIPTION UNITS Address / Control Setup Time SYSCLK Address / Control Pulse Width 16*T SYSCLK SYSCLK Address / Control Hold Time SYSCLK Address Latch Enable High Time ALEH SYSCLK... - Page 214 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
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Page 215: Port Input/Output
The C8051F12x family of devices are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (C8051F120/2/4/6) or 32 digital I/O pins (C8051F121/3/5/7), organized as 8-bit Ports. All ports are both bit- and byte-addressable through their corresponding Port Data registers. All Port pins are 5 V-tolerant, and all support con- figurable Open-Drain or Push-Pull output modes and weak pull-ups. -
Page 216: Figure 19.2. Port I/O Functional Block Diagram
C8051F120/1/2/3/4/5/6/7 The C8051F12x family of devices have a wide array of digital resources which are available through the four lower I/ O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 19.2. -
Page 217: Ports 0 Through 3 And The Priority Crossbar Decoder
C8051F120/1/2/3/4/5/6/7 19.1. Ports 0 through 3 and the Priority Crossbar Decoder The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in order starting with P0.0 and continue through P3.7 if necessary. -
Page 218: Configuring The Output Modes Of The Port Pins
C8051F120/1/2/3/4/5/6/7 ble at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to assign TX0 to a Port pin without assigning RX0 as well. -
Page 219: Configuring Port Pins As Digital Inputs
C8051F120/1/2/3/4/5/6/7 19.1.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting P3MDOUT.7 to a logic 0 and P3.7 to a logic 1. -
Page 220: External Memory Interface Pin Assignments
C8051F120/1/2/3/4/5/6/7 19.1.6. External Memory Interface Pin Assignments If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.5) should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Mem- ory Interface is in Multiplexed mode, P0.5 (ALE). -
Page 221: Figure 19.5. Priority Crossbar Decode Table
C8051F120/1/2/3/4/5/6/7 Figure 19.5. Priority Crossbar Decode Table Crossbar Register Bits PIN I/O 0 UART0EN: XBR0.2 MISO SPI0EN: XBR0.1 MOSI NSS is not assigned to a port pin when the SPI is placed in 3-wire mode SMB0EN: XBR0.0 UART1EN: XBR2.2 CEX0... -
Page 222: Crossbar Pin Assignment Example
C8051F120/1/2/3/4/5/6/7 19.1.7. Crossbar Pin Assignment Example In this example (Figure 19.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, / INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in Multiplexed mode and to appear on the Low ports. -
Page 223: Figure 19.6. Crossbar Example
C8051F120/1/2/3/4/5/6/7 Figure 19.6. Crossbar Example: (EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xE3; Crossbar Register Bits PIN I/O 0 UART0EN: XBR0.2 MISO SPI0EN: XBR0.1 MOSI SMB0EN: XBR0.0 UART1EN: XBR2.2 CEX0 CEX1 CEX2 PCA0ME: XBR0.[5:3] CEX3 CEX4 CEX5 ECI0E: XBR0.6 CP0E: XBR0.7... -
Page 224: Figure 19.7. Xbr0: Port I/O Crossbar Register 0
C8051F120/1/2/3/4/5/6/7 Figure 19.7. XBR0: Port I/O Crossbar Register 0 Reset Value CP0E ECI0E PCA0ME UART0EN SPI0EN SMB0EN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 SFR Page: Bit7: CP0E: Comparator 0 Output Enable Bit. 0: CP0 unavailable at Port pin. -
Page 225: Figure 19.8. Xbr1: Port I/O Crossbar Register 1
C8051F120/1/2/3/4/5/6/7 Figure 19.8. XBR1: Port I/O Crossbar Register 1 Reset Value SYSCKE T2EXE INT1E INT0E CP1E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE2 SFR Page: Bit7: SYSCKE: /SYSCLK Output Enable Bit. 0: /SYSCLK unavailable at Port pin. -
Page 226: Figure 19.9. Xbr2: Port I/O Crossbar Register 2
C8051F120/1/2/3/4/5/6/7 Figure 19.9. XBR2: Port I/O Crossbar Register 2 Reset Value WEAKPUD XBARE CNVST2E T4EXE UART1E EMIFLE CNVST0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE3 SFR Page: Bit7: WEAKPUD: Weak Pull-Up Disable Bit. 0: Weak pull-ups globally enabled. -
Page 227: Figure 19.10. P0: Port0 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.10. P0: Port0 Data Register Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0x80 SFR Page: All Pages Bits7-0: P0.[7:0]: Port0 Output Latch Bits. -
Page 228: Figure 19.12. P1: Port1 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.12. P1: Port1 Data Register Reset Value P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0x90 SFR Page: All Pages Bits7-0: P1.[7:0]: Port1 Output Latch Bits. -
Page 229: Figure 19.14. P1Mdout: Port1 Output Mode Register
C8051F120/1/2/3/4/5/6/7 Figure 19.14. P1MDOUT: Port1 Output Mode Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA5 SFR Page: Bits7-0: P1MDOUT.[7:0]: Port1 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. -
Page 230: Figure 19.16. P2Mdout: Port2 Output Mode Register
C8051F120/1/2/3/4/5/6/7 Figure 19.16. P2MDOUT: Port2 Output Mode Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 SFR Page: Bits7-0: P2MDOUT.[7:0]: Port2 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. -
Page 231: Ports 4 Through 7 (C8051F120/2/4/6 Only)
0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. 19.2. Ports 4 through 7 (C8051F120/2/4/6 only) All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 19.19, Figure 19.21, Figure 19.23, and Figure 19.25), a set of SFR’s which... -
Page 232: Configuring Port Pins As Digital Inputs
C8051F120/1/2/3/4/5/6/7 19.2.3. Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting P7MDOUT.7 to a logic 0 and P7.7 to a logic 1. -
Page 233: Figure 19.19. P4: Port4 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.19. P4: Port4 Data Register Reset Value P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xC8 SFR Page: Bits7-0: P4.[7:0]: Port4 Output Latch Bits. Write - Output appears on I/O pins. -
Page 234: Figure 19.21. P5: Port5 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.21. P5: Port5 Data Register Reset Value P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xD8 SFR Page: Bits7-0: P5.[7:0]: Port5 Output Latch Bits. Write - Output appears on I/O pins. -
Page 235: Figure 19.23. P6: Port6 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.23. P6: Port6 Data Register Reset Value P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xE8 SFR Page: Bits7-0: P6.[7:0]: Port6 Output Latch Bits. Write - Output appears on I/O pins. -
Page 236: Figure 19.25. P7: Port7 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 19.25. P7: Port7 Data Register Reset Value P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xF8 SFR Page: Bits7-0: P7.[7:0]: Port7 Output Latch Bits. Write - Output appears on I/O pins. -
Page 237: System Management Bus / I2C Bus (Smbus0)
C8051F120/1/2/3/4/5/6/7 SYSTEM MANAGEMENT BUS / I C BUS (SMBUS0) The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage- ment Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the data. -
Page 238: Supporting Documents
C8051F120/1/2/3/4/5/6/7 and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free. -
Page 239: Arbitration
C8051F120/1/2/3/4/5/6/7 tion from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. -
Page 240: Smbus Transfer Modes
C8051F120/1/2/3/4/5/6/7 20.3. SMBus Transfer Modes The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. -
Page 241: Slave Transmitter Mode
C8051F120/1/2/3/4/5/6/7 20.3.3. Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave address matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. -
Page 242: Smbus Special Function Registers
C8051F120/1/2/3/4/5/6/7 20.4. SMBus Special Function Registers The SMBus0 serial interface is accessed and controlled through five SFR’s: SMB0CN Control Register, SMB0CR Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The five special function registers related to the operation of the SMBus0 interface are described in the following sec- tions. -
Page 243: Figure 20.8. Smb0Cn: Smbus0 Control Register
C8051F120/1/2/3/4/5/6/7 generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 20.9, SMBus0 Clock Rate Register). When the TOE bit in SMB0CN is set to logic 1, Timer 3 is used to detect SCL low timeouts. If Timer 3 is enabled (see Section “24.2. -
Page 244: Clock Rate Register
C8051F120/1/2/3/4/5/6/7 20.4.2. Clock Rate Register Figure 20.9. SMB0CR: SMBus0 Clock Rate Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCF SFR Page: Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. -
Page 245: Data Register
C8051F120/1/2/3/4/5/6/7 20.4.3. Data Register The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software can read or write to this register while the SI flag is set to logic 1; software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag reads logic 0 since the hardware may be in the pro- cess of shifting a byte of data in or out of the register. -
Page 246: Status Register
C8051F120/1/2/3/4/5/6/7 20.4.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when SI = ‘1’. -
Page 247: Table 20.1.Smb0Sta Status Codes And States
C8051F120/1/2/3/4/5/6/7 Table 20.1. SMB0STA Status Codes and States Status Mode SMBus State Typical Action Code 0x08 START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. 0x10 Repeated START condition transmitted. Load SMB0DAT with Slave Address + R/W. Clear STA. - Page 248 C8051F120/1/2/3/4/5/6/7 Table 20.1. SMB0STA Status Codes and States Status Mode SMBus State Typical Action Code 0x60 Own slave address + W received. ACK trans- Wait for data. mitted. 0x68 Arbitration lost in sending SLA + R/W as mas- Save current data for retry when bus is ter.
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Page 249: Enhanced Serial Peripheral Interface (Spi0)
C8051F120/1/2/3/4/5/6/7 ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. -
Page 250: Signal Descriptions
C8051F120/1/2/3/4/5/6/7 21.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 21.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. -
Page 251: Spi0 Master Mode Operation
C8051F120/1/2/3/4/5/6/7 21.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. -
Page 252: Figure 21.2. Multiple-Master Mode Connection Diagram
C8051F120/1/2/3/4/5/6/7 Figure 21.2. Multiple-Master Mode Connection Diagram GPIO MISO MISO Master Master MOSI MOSI Device 1 Device 2 GPIO Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Slave Device Device MISO MISO MOSI MOSI Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram... -
Page 253: Spi0 Slave Mode Operation
C8051F120/1/2/3/4/5/6/7 21.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. -
Page 254: Serial Clock Timing
C8051F120/1/2/3/4/5/6/7 21.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configu- ration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). -
Page 255: Figure 21.6. Slave Mode Data/Clock Timing (Ckpha = 0)
C8051F120/1/2/3/4/5/6/7 Figure 21.6. Slave Mode Data/Clock Timing (CKPHA = 0) (CKPOL=0, CKPHA=0) (CKPOL=1, CKPHA=0) MOSI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 6 Bit 5 Bit 4 Bit 3 Bit 2... -
Page 256: Spi Special Function Registers
C8051F120/1/2/3/4/5/6/7 21.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg- ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. -
Page 257: Figure 21.9. Spi0Cn: Spi0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 21.9. SPI0CN: SPI0 Control Register Reset Value SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN 00000110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xF8 SFR Page: Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. -
Page 258: Figure 21.10. Spi0Ckr: Spi0 Clock Rate Register
C8051F120/1/2/3/4/5/6/7 Figure 21.10. SPI0CKR: SPI0 Clock Rate Register Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9D SFR Page: Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. -
Page 259: Figure 21.11. Spi0Dat: Spi0 Data Register
C8051F120/1/2/3/4/5/6/7 Figure 21.11. SPI0DAT: SPI0 Data Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9B SFR Page: Bits 7-0: SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. -
Page 260: Figure 21.12. Spi Master Timing (Ckpha = 0)
C8051F120/1/2/3/4/5/6/7 Figure 21.12. SPI Master Timing (CKPHA = 0) SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.13. SPI Master Timing (CKPHA = 1) SCK*... -
Page 261: Figure 21.14. Spi Slave Timing (Ckpha = 0)
C8051F120/1/2/3/4/5/6/7 Figure 21.14. SPI Slave Timing (CKPHA = 0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.15. SPI Slave Timing (CKPHA = 1) SCK* MOSI MISO * SCK is shown for CKPOL = 0. -
Page 262: Table 21.1.Spi Slave Timing Parameters
C8051F120/1/2/3/4/5/6/7 Table 21.1. SPI Slave Timing Parameters PARAMETER DESCRIPTION UNITS † MASTER MODE TIMING (See Figure 21.12 and Figure 21.13) SCK High Time MCKH SYSCLK SCK Low Time MCKL SYSCLK MISO Valid to SCK Shift Edge + 20 SYSCLK SCK Shift Edge to MISO Change †... -
Page 263: Uart0
C8051F120/1/2/3/4/5/6/7 UART0 UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup- ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. -
Page 264: Uart0 Operational Modes
C8051F120/1/2/3/4/5/6/7 22.1. UART0 Operational Modes UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the SCON0 register. These four modes offer different baud rates and communication protocols. The four modes are summarized in Table 22.1. -
Page 265: Mode 1: 8-Bit Uart, Variable Baud Rate
C8051F120/1/2/3/4/5/6/7 22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin. -
Page 266: Mode 2: 9-Bit Uart, Fixed Baud Rate
C8051F120/1/2/3/4/5/6/7 22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and... -
Page 267: Mode 3: 9-Bit Uart, Variable Baud Rate
C8051F120/1/2/3/4/5/6/7 Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram RS-232 RS-232 C8051Fxxx LEVEL XLTR C8051Fxxx 22.1.4. Mode 3: 9-Bit UART, Variable Baud Rate Mode 3 uses the Mode 2 transmission protocol with the Mode 1 baud rate generation. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. -
Page 268: Multiprocessor Communications
C8051F120/1/2/3/4/5/6/7 22.2. Multiprocessor Communications Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in UART0 address recognition hardware. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). -
Page 269: Frame And Transmission Error Detection
C8051F120/1/2/3/4/5/6/7 Figure 22.7. UART Multi-Processor Mode Interconnect Diagram Master Slave Slave Slave Device Device Device Device 22.3. Frame and Transmission Error Detection All Modes: The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the SBUF0 reg- ister while a transmit is in progress. -
Page 270: Table 22.2.Oscillator Frequencies For Standard Baud Rates
C8051F120/1/2/3/4/5/6/7 Table 22.2. Oscillator Frequencies for Standard Baud Rates System Clock Frequency Divide Factor Timer 1 Reload Timer 2, 3, or 4 Resulting Baud Rate (Hz)** (MHz) Value* Reload Value 100.0 0xCA 0xFFCA 115200 (115741) 99.5328 0xCA 0xFFCA 115200 50.0... -
Page 271: Figure 22.8. Scon0: Uart0 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 22.8. SCON0: UART0 Control Register Reset Value SM00 SM10 SM20 REN0 TB80 RB80 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0x98 SFR Page: Bits7-6: SM00-SM10: Serial Port Operation Mode: Write: When written, these bits select the Serial Port Operation Mode as follows:... -
Page 272: Figure 22.9. Ssta0: Uart0 Status And Clock Selection Register
C8051F120/1/2/3/4/5/6/7 Figure 22.9. SSTA0: UART0 Status and Clock Selection Register Reset Value RXOV0 TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x91 SFR Page: † Bit7: FE0: Frame Error Flag. This flag indicates if an invalid (low) STOP bit is detected. -
Page 273: Figure 22.10. Sbuf0: Uart0 Data Buffer Register
C8051F120/1/2/3/4/5/6/7 Figure 22.10. SBUF0: UART0 Data Buffer Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x99 SFR Page: Bits7-0: SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB) This is actually two registers; a transmit and a receive buffer register. When data is moved to SBUF0, it goes to the transmit buffer and is held for serial transmission. - Page 274 C8051F120/1/2/3/4/5/6/7 Notes Rev. 1.2...
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Page 275: Uart1
C8051F120/1/2/3/4/5/6/7 UART1 UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “23.1. Enhanced Baud Rate Generation” on page 276). -
Page 276: Enhanced Baud Rate Generation
C8051F120/1/2/3/4/5/6/7 23.1. Enhanced Baud Rate Generation The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. -
Page 277: Operational Modes
C8051F120/1/2/3/4/5/6/7 23.2. Operational Modes UART1 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S1MODE bit (SCON1.7). Typical UART connection options are shown below. Figure 23.3. UART Interconnect Diagram RS-232 RS-232 C8051Fxxx LEVEL... -
Page 278: 9-Bit Uart
C8051F120/1/2/3/4/5/6/7 23.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81 (SCON1.3), which is assigned by user software. -
Page 279: Multiprocessor Communications
C8051F120/1/2/3/4/5/6/7 23.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). -
Page 280: Figure 23.7. Scon1: Serial Port 1 Control Register
C8051F120/1/2/3/4/5/6/7 Figure 23.7. SCON1: Serial Port 1 Control Register Reset Value S1MODE MCE1 REN1 TB81 RB81 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0x98 SFR Page: Bit7: S1MODE: Serial Port 1 Operation Mode. This bit selects the UART1 Operation Mode. -
Page 281: Figure 23.8. Sbuf1: Serial (Uart1) Port Data Buffer Register
C8051F120/1/2/3/4/5/6/7 Figure 23.8. SBUF1: Serial (UART1) Port Data Buffer Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x99 SFR Page: Bits7-0: SBUF1[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF1, it goes to the transmit shift register and is held for serial transmission. -
Page 282: Table 23.1.Timer Settings For Standard Baud Rates Using The Internal Oscillator
C8051F120/1/2/3/4/5/6/7 Table 23.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Frequency: 24.5 MHz Target Baud Rate Oscillator Timer Clock SCA1-SCA0 Timer 1 † Baud Rate % Error Divide Source Reload † (pre-scale select) (bps) Factor Value (hex) 230400 -0.32%... -
Page 283: Table 23.3.Timer Settings For Standard Baud Rates Using An External Oscillator
C8051F120/1/2/3/4/5/6/7 Table 23.3. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 22.1184 MHz Target Baud Rate Oscillator Timer Clock SCA1-SCA0 Timer 1 † Baud Rate % Error Divide Source Reload † (pre-scale select) (bps) Factor Value (hex) 230400 0.00%... -
Page 284: Table 23.5.Timer Settings For Standard Baud Rates Using The Pll
C8051F120/1/2/3/4/5/6/7 Table 23.5. Timer Settings for Standard Baud Rates Using the PLL Frequency: 100.0 MHz Target Baud Rate Oscillator Timer Clock SCA1-SCA0 Timer 1 † Baud Rate % Error Divide Source Reload † (pre-scale select) (bps) Factor Value (hex) 230400 -0.01%... -
Page 285: Timers
C8051F120/1/2/3/4/5/6/7 TIMERS Each MCU includes 5 counter/timers: Timer 0 and Timer 1 are 16-bit counter/timers compatible with those found in the standard 8051. Timer 2, Timer 3, and Timer 4 are 16-bit auto-reload and capture counter/timers for use with the ADC, DAC’s, square-wave generation, or for general-purpose use. -
Page 286: Mode 1: 16-Bit Counter/Timer
C8051F120/1/2/3/4/5/6/7 clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see Figure 24.6). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is logic-level 1. -
Page 287: Mode 2: 8-Bit Counter/Timer With Auto-Reload
C8051F120/1/2/3/4/5/6/7 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. -
Page 288: Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)
C8051F120/1/2/3/4/5/6/7 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. -
Page 289: Figure 24.4. Tcon: Timer Control Register
C8051F120/1/2/3/4/5/6/7 Figure 24.4. TCON: Timer Control Register Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable 0x88 SFR Address: SFR Page: Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. -
Page 290: Figure 24.5. Tmod: Timer Mode Register
C8051F120/1/2/3/4/5/6/7 Figure 24.5. TMOD: Timer Mode Register Reset Value GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x89 SFR Address: SFR Page: Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. -
Page 291: Figure 24.6. Ckcon: Clock Control Register
C8051F120/1/2/3/4/5/6/7 Figure 24.6. CKCON: Clock Control Register Reset Value SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x8E SFR Address: SFR Page: Bits7-5: UNUSED. Read = 000b, Write = don’t care. Bit4: T1M: Timer 1 Clock Select. -
Page 292: Figure 24.7. Tl0: Timer 0 Low Byte
C8051F120/1/2/3/4/5/6/7 Figure 24.7. TL0: Timer 0 Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x8A SFR Address: SFR Page: Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. -
Page 293: Timer 2, Timer 3, And Timer 4
C8051F120/1/2/3/4/5/6/7 24.2. Timer 2, Timer 3, and Timer 4 Timers 2, 3, and 4 are 16-bit counter/timers, each formed by two 8-bit SFR’s: TMRnL (low byte) and TMRnH (high byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. Timers 2 and 4 feature auto-reload, capture, and toggle output modes with the ability to count up or down. -
Page 294: Capture Mode
C8051F120/1/2/3/4/5/6/7 24.2.2. Capture Mode In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the Timer Exter- nal Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX input pin (Timer 3 shares the T2EX pin with Timer 2) causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers (RCAPnH, RCAPnL). -
Page 295: Auto-Reload Mode
C8051F120/1/2/3/4/5/6/7 24.2.3. Auto-Reload Mode In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/Capture Registers (RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. - Page 296 C8051F120/1/2/3/4/5/6/7 the timer and the values loaded into RCAPnH and RCAPnL. When counting DOWN, the auto-reload value for the timer is 0xFFFF, and underflow will occur when the value in the timer matches the value stored in RCAPnH:RCAPnL. When counting UP, the auto-reload value for the timer is RCAPnH:RCAPnL, and overflow will occur when the value in the timer transitions from 0xFFFF to the reload value.
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Page 297: Figure 24.13. Tmrncn: Timer 2, 3, And 4 Control Registers
C8051F120/1/2/3/4/5/6/7 Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers Reset Value EXFn EXENn C/Tn CP/RLn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: TMR2CN:0xC8;TMR3CN:0xC8;TMR4CN:0xC8 SFR Page: TMR2CN: page 0;TMR3CN: page 1;TMR4CN: page 2 Bit7: TFn: Timer 2, 3, and 4 Overflow/Underflow Flag. -
Page 298: Figure 24.14. Tmrncf: Timer 2, 3, And 4 Configuration Registers
C8051F120/1/2/3/4/5/6/7 Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers Reset Value TnM1 TnM0 TOGn TnOE DCEN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9 SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: Page 2 Bit7-5: Reserved. -
Page 299: Figure 24.15. Rcapnl: Timer 2, 3, And 4 Capture Register Low Byte
C8051F120/1/2/3/4/5/6/7 Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: RCAP2L: 0xCA; RCAP3L: 0xCA; RCAP4L: 0xCA SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2 Bits 7-0: RCAP2, 3, and 4L: Timer 2, 3, and 4 Capture Register Low Byte. -
Page 300: Figure 24.18. Tmrnh Timer 2, 3, And 4 High Byte
C8051F120/1/2/3/4/5/6/7 Figure 24.18. TMRnH Timer 2, 3, and 4 High Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2H: 0xCD; TMR3H: 0xCD; TMR4H: 0xCD SFR Page: TMR2H: page 0; TMR3H: page 1; TMR4H: page 2 Bits 7-0: TH2, 3, and 4: Timer 2, 3, and 4 High Byte. -
Page 301: Programmable Counter Array
C8051F120/1/2/3/4/5/6/7 PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU interven- tion than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/ compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “19.1. -
Page 302: Pca Counter/Timer
C8051F120/1/2/3/4/5/6/7 25.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot”... -
Page 303: Capture/Compare Modules
C8051F120/1/2/3/4/5/6/7 25.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modu- lator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. -
Page 304: Edge-Triggered Capture Mode
C8051F120/1/2/3/4/5/6/7 25.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to- high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). -
Page 305: Software Timer (Compare) Mode
C8051F120/1/2/3/4/5/6/7 25.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA0 counter/timer is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. -
Page 306: High Speed Output Mode
C8051F120/1/2/3/4/5/6/7 25.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode. -
Page 307: Frequency Output Mode
C8051F120/1/2/3/4/5/6/7 25.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 25.1. -
Page 308: 8-Bit Pulse Width Modulator Mode
C8051F120/1/2/3/4/5/6/7 25.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. -
Page 309: 16-Bit Pulse Width Modulator Mode
C8051F120/1/2/3/4/5/6/7 25.2.6. 16-Bit Pulse Width Modulator Mode Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module contents, the output on CEXn is asserted high;... -
Page 310: Register Descriptions For Pca0
C8051F120/1/2/3/4/5/6/7 25.3. Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of PCA0. Figure 25.10. PCA0CN: PCA Control Register Reset Value CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 00000000 Bit7 Bit6 Bit5 Bit4... -
Page 311: Figure 25.11. Pca0Md: Pca0 Mode Register
C8051F120/1/2/3/4/5/6/7 Figure 25.11. PCA0MD: PCA0 Mode Register Reset Value CIDL CPS2 CPS1 CPS0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD9 SFR Page: Bit7: CIDL: PCA0 Counter/Timer Idle Control. Specifies PCA0 behavior when CPU is in Idle Mode. -
Page 312: Figure 25.12. Pca0Cpmn: Pca0 Capture/Compare Mode Registers
C8051F120/1/2/3/4/5/6/7 Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC, PCA0CPM3: 0xDD, PCA0CPM4: 0xDE, PCA0CPM5: 0xDF... -
Page 313: Figure 25.13. Pca0L: Pca0 Counter/Timer Low Byte
C8051F120/1/2/3/4/5/6/7 Figure 25.13. PCA0L: PCA0 Counter/Timer Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF9 SFR Page: Bits 7-0: PCA0L: PCA0 Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA0 Counter/Timer. -
Page 314: Figure 25.15. Pca0Cpln: Pca0 Capture Module Low Byte
C8051F120/1/2/3/4/5/6/7 Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPL0: 0xFB, PCA0CPL1: 0xFD, PCA0CPL2: 0xE9, PCA0CPL3: 0xEB, PCA0CPL4: 0xED, PCA0CPL5: 0xE1 SFR Page: PCA0CPL0: page 0, PCA0CPL1: page 0, PCA0CPL2: page 0, PCA0CPL3: page 0, PCA0CPL4: page 0, PCA0CPL5: page 0 Bits7-0: PCA0CPLn: PCA0 Capture Module Low Byte. -
Page 315: Jtag (Ieee 1149.1)
C8051F120/1/2/3/4/5/6/7 JTAG (IEEE 1149.1) Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan Architecture. -
Page 316: Boundary Scan
Update Reset output to /RST pin (C8051F121/3/5/7 devices) Capture Reset Enable from MCU (C8051F120/2/4/6 devices) Update Reset Enable to /RST pin (C8051F120/2/4/6 devices) Capture Reset input from /RST pin (C8051F120/2/4/6 devices) Update Reset output to /RST pin (C8051F120/2/4/6 devices) Capture... -
Page 317: Extest Instruction
Figure 26.2. DEVICEID: JTAG Device ID Register Reset Value Version Part Number Manufacturer ID 0xn0003243 Bit31 Bit28 Bit27 Bit12 Bit11 Bit1 Bit0 Version = 0000b Part Number = 0000 0000 0000 0111b (C8051F120/1/2/3/4/5/6/7) Manufacturer ID = 0010 0100 001b (Silicon Labs) Rev. 1.2... - Page 318 C8051F120/1/2/3/4/5/6/7 26.2. Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register. Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register.
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Page 319: Figure 26.3. Flashcon: Jtag Flash Control Register
C8051F120/1/2/3/4/5/6/7 Figure 26.3. FLASHCON: JTAG Flash Control Register Reset Value SFLE WRMD2 WRMD1 WRMD0 RDMD3 RDMD2 RDMD1 RDMD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT Register. -
Page 320: Figure 26.4. Flashdat: Jtag Flash Data Register
C8051F120/1/2/3/4/5/6/7 Figure 26.5. FLASHADR: JTAG Flash Address Register Reset Value 0x00000 Bit16 Bit0 This register holds the address for all JTAG Flash read, write, and erase operations. This register autoincrements after each read or write, regardless of whether the operation succeeded or failed. - Page 321 (IDE) which has a debugger and integrated 8051 assembler. The kit also includes an RS-232 to JTAG interface mod- ule referred to as the Serial Adapter. There is also a target application board with a C8051F120 installed. RS-232 and JTAG cables and wall-mount power supply are also included.
- Page 322 Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any prod- uct or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
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