Silicon Laboratories EFM8 Series Manuals

Manuals and User Guides for Silicon Laboratories EFM8 Series. We have 2 Silicon Laboratories EFM8 Series manuals available for free PDF download: Reference Manual, Programming Manual

Silicon Laboratories EFM8 Series Reference Manual (362 pages)

EFM8 Universal Bee Family

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 3 MB

Table of Contents
2
VBUS Control
12
1 System Overview

13
- Introduction
  13
- Power
  14
- I/O
  14
- Clocking
  15
- Counters/Timers and PWM
  15
- Communications and Other Digital Peripherals
  17
  - Basic Data Transfer
    18
- Analog
  19
- Reset Sources
  20
- Debugging
  20
- Bootloader
  21
2 Memory

23
- Memory Organization
  23
- Program Memory
  23
- Data Memory
  23
- Memory Map
  25
- XRAM Control Registers
  27
  - EMI0CN: External Memory Interface Control
    27
3 Special Function Registers

28
- Special Function Register Access
  28
- Special Function Register Memory Map
  30
  - FADDR: USB0 Function Address
    31
- SFR Access Control Registers
  37
  - SFRPAGE: SFR Page
    37
  - ADC0 Control Registers
    37
  - Sfrpgcn: Sfr
    38
  - Sfrstack: Sfr
    38
4 Flash Memory

39
- Introduction
  39
- Features
  39
- Functional Description
  40
- Flash Control Registers
  43
  - PSCTL: Program Store Control
    43
  - FLKEY: Flash Lock and Key
    44
5 Device Identification

45
- Unique Identifier
  45
- Device Identification Registers
  45
6 Interrupts

47
7 Power Management and Internal Regulators

62
- Introduction
  62
- Features
  63
- Idle Mode
  64
- Stop Mode
  64
- Suspend Mode
  64
- Snooze Mode
  65
- Shutdown Mode
  65
- To-3.3V Regulator
  65
- Power Management Control Registers
  66
8 Clocking and Oscillators

71
9 Reset Sources and Power Supply Monitor

77
- Introduction
  77
- Features
  77
- Functional Description
  78
  - Device Reset
    78
  - Power-On Reset
    79
  - Supply Monitor Reset
    80
  - External Reset
    80
  - Missing Clock Detector Reset
    80
  - Comparator (CMP0) Reset
    81
  - Watchdog Timer Reset
    81
  - Flash Error Reset
    81
  - Software Reset
    81
  - USB Reset
    81
- Reset Sources and Supply Monitor Control Registers
  82
  - RSTSRC: Reset Source
    82
  - VDM0CN: Supply Monitor Control
    83
10 Microcontroller Core

84
- Introduction
  84
- Features
  85
- Functional Description
  85
  - Programming and Debugging Support
    85
  - Prefetch Engine
    85
  - Instruction Set
    86
- CPU Core Registers
  90
  - DPL: Data Pointer Low
    90
  - DPH: Data Pointer High
    90
  - SP: Stack Pointer
    90
  - ACC: Accumulator
    91
  - B: B Register
    91
  - PSW: Program Status Word
    92
  - PFE0CN: Prefetch Engine Control
    93
11 Port I/O, Crossbar, External Interrupts, and Port Match

94
- Introduction
  94
- Features
  94
  - Functional Description
    95
    
    Port I/O Modes of Operation
    95
    
    Analog and Digital Functions
    96
    
    Priority Crossbar Decoder
    98
    
    INT0 and INT1
    100
    
    Port Match
    100
    
    Direct Port I/O Access (Read/Write)
    100
  - Port I/O Control Registers
    101
    
    XBR0: Port I/O Crossbar
    101
    
    XBR1: Port I/O Crossbar 1
    103
    
    XBR2: Port I/O Crossbar 2
    104
    
    PRTDRV: Port Drive Strength
    105
    
    P0MASK: Port 0 Mask
    106
    
    P0MAT: Port 0 Match
    107
    
    P0: Port 0 Pin Latch
    108
    
    P0MDIN: Port 0 Input Mode
    109
    
    P0MDOUT: Port 0 Output Mode
    110
    
    P0SKIP: Port 0 Skip
    111
    
    P1MASK: Port 1 Mask
    112
    
    P1MAT: Port 1 Match
    113
    
    P1: Port 1 Pin Latch
    114
    
    P1MDIN: Port 1 Input Mode
    115
    
    P1MDOUT: Port 1 Output Mode
    116
    
    P1SKIP: Port 1 Skip
    117
    
    P2MASK: Port 2 Mask
    118
    
    P2MAT: Port 2 Match
    118
    
    P2: Port 2 Pin Latch
    119
    
    P2MDIN: Port 2 Input Mode
    119
    
    P2MDOUT: Port 2 Output Mode
    120
  - INT0 and INT1 Control Registers
    121
    
    IT01CF: INT0/INT1 Configuration
    121
12 Analog-To-Digital Converter (ADC0)

123
- Introduction
  123
- Features
  124
- Functional Description
  124
  - Clocking
    124
  - Voltage Reference Options
    124
  - Input Selection
    125
  - Gain Setting
    126
  - Initiating Conversions
    126
  - Input Tracking
    126
  - Burst Mode
    129
  - 8-Bit Mode
    129
  - 12-Bit Mode
    130
  - Output Formatting
    131
  - Power Considerations
    132
  - Window Comparator
    134
  - Temperature Sensor
    136
  - ADC0CN0: ADC0 Control 0
    137
  - ADC0 Control Registers 1
    137
  - ADC0CN1: ADC0 Control 1
    138
  - ADC0CF: ADC0 Configuration
    139
  - ADC0AC: ADC0 Accumulator Configuration
    140
  - ADC0PWR: ADC0 Power Control
    142
  - ADC0TK: ADC0 Burst Mode Track Time
    143
  - ADC0H: ADC0 Data Word High Byte
    143
  - ADC0L: ADC0 Data Word Low Byte
    144
  - ADC0GTH: ADC0 Greater-Than High Byte
    144
  - ADC0GTL: ADC0 Greater-Than Low Byte
    144
  - ADC0LTH: ADC0 Less-Than High Byte
    145
  - ADC0LTL: ADC0 Less-Than Low Byte
    145
  - ADC0MX: ADC0 Multiplexer Selection
    145
  - REF0CN: Voltage Reference Control
    146
13 Comparators (CMP0 and CMP1)

147
- Introduction
  147
- Features
  147
- Functional Description
  148
  - Response Time and Supply Current
    148
  - Hysteresis
    148
  - Input Selection
    148
  - Output Routing
    153
  - CMP0 Control Registers
    155
    
    CMP0CN0: Comparator 0 Control 0
    155
    
    CMP0MD: Comparator 0 Mode
    157
    
    CMP0MX: Comparator 0 Multiplexer Selection
    158
    
    CMP0CN1: Comparator 0 Control 1
    159
  - CMP1 Control Registers
    160
    
    CMP1CN0: Comparator 1 Control 0
    160
    
    CMP1MD: Comparator 1 Mode
    162
    
    CMP1MX: Comparator 1 Multiplexer Selection
    163
    
    CMP1CN1: Comparator 1 Control 1
    164
14 Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)

165
15 Cyclic Redundancy Check (CRC0)

182
- Introduction
  182
- Features
  182
- Functional Description
  183
  - 16-Bit CRC Algorithm
    183
  - Using the CRC on a Data Stream
    184
  - Using the CRC to Check Code Memory
    184
  - Bit Reversal
    184
  - CRC0 Control Registers
    185
    
    CRC0CN0: CRC0 Control 0
    185
    
    CRC0IN: CRC0 Data Input
    185
    
    CRC0DAT: CRC0 Data Output
    186
    
    CRC0ST: CRC0 Automatic Flash Sector Start
    186
    
    CRC0CNT: CRC0 Automatic Flash Sector Count
    186
    
    CRC0FLIP: CRC0 Bit Flip
    187
    
    CRC0CN1: CRC0 Control 1
    187
16 Programmable Counter Array (PCA0)

188
- Introduction
  188
- Features
  189
- Functional Description
  189
  - Counter / Timer
    189
  - Interrupt Sources
    190
  - Capture/Compare Modules
    190
  - Edge-Triggered Capture Mode
    191
  - Software Timer (Compare) Mode
    192
  - High-Speed Output Mode
    193
  - Frequency Output Mode
    194
  - PWM Waveform Generation
    194
  - PCA0 Control Registers
    201
    
    PCA0CN0: PCA Control
    201
    
    PCA0MD: PCA Mode
    202
    
    PCA0PWM: PCA PWM Configuration
    203
    
    PCA0CLR: PCA Comparator Clear Control
    204
    
    PCA0L: PCA Counter/Timer Low Byte
    204
    
    PCA0H: PCA Counter/Timer High Byte
    205
    
    PCA0POL: PCA Output Polarity
    205
    
    PCA0CENT: PCA Center Alignment Enable
    206
    
    PCA0CPM0: PCA Channel 0 Capture/Compare Mode
    207
    
    PCA0CPL0: PCA Channel 0 Capture Module Low Byte
    208
    
    PCA0CPH0: PCA Channel 0 Capture Module High Byte
    208
    
    PCA0CPM1: PCA Channel 1 Capture/Compare Mode
    209
    
    PCA0CPL1: PCA Channel 1 Capture Module Low Byte
    210
    
    PCA0CPH1: PCA Channel 1 Capture Module High Byte
    210
    
    PCA0CPM2: PCA Channel 2 Capture/Compare Mode
    211
    
    PCA0CPL2: PCA Channel 2 Capture Module Low Byte
    212
    
    PCA0CPH2: PCA Channel 2 Capture Module High Byte
    212
17 Serial Peripheral Interface (SPI0)

213
- Introduction
  213
- Features
  213
- Functional Description
  214
  - Signals
    214
  - Master Mode Operation
    215
  - Slave Mode Operation
    216
  - Clock Phase and Polarity
    217
  - Using the SPI Fifos
    218
  - Basic Data Transfer 2
    218
  - SPI Timing Diagrams
    221
  - SPI0 Control Registers
    224
    
    SPI0CFG: SPI0 Configuration
    224
    
    SPI0CN0: SPI0 Control
    226
    
    SPI0CKR: SPI0 Clock Rate
    227
    
    SPI0DAT: SPI0 Data
    227
    
    SPI0FCN0: SPI0 FIFO Control
    228
    
    SPI0FCN1: SPI0 FIFO Control
    228
    
    SPI0FCT: SPI0 FIFO Count
    230
    
    SPI0PCF: SPI0 Pin Configuration
    231
18 System Management Bus / I2C (SMB0)

232
- Introduction
  232
- Features
  232
- Functional Description
  232
  - Supporting Documents
    232
  - Smbus Protocol
    233
  - Configuring the Smbus Module
    235
  - Operational Modes
    240
  - SMB0 Control Registers
    248
    
    SMB0CF: Smbus 0 Configuration
    248
    
    SMB0TC: Smbus 0 Timing and Pin Control
    249
    
    SMB0CN0: Smbus 0 Control
    250
    
    SMB0ADR: Smbus 0 Slave Address
    251
    
    SMB0ADM: Smbus 0 Slave Address Mask
    252
    
    SMB0DAT: Smbus 0 Data
    252
    
    SMB0FCN0: Smbus 0 FIFO Control
    253
    
    SMB0FCN1: Smbus 0 FIFO Control
    254
    
    SMB0RXLN: Smbus 0 Receive Length Counter
    255
    
    SMB0FCT: Smbus 0 FIFO Count
    255
19 Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5)

256
- Introduction
  256
- Features
  256
- Functional Description
  257
  - System Connections
    257
  - Timer 0 and Timer 1
    258
  - Timer 2, Timer 3, Timer 4, and Timer 5
    262
  - Timer 0, 1, 2, 3, 4, and 5 Control Registers
    268
    
    CKCON0: Clock Control
    268
    
    CKCON1: Clock Control
    270
    
    TCON: Timer 0/1 Control
    271
    
    TMOD: Timer 0/1 Mode
    272
    
    TL0: Timer 0 Low Byte
    273
    
    TL1: Timer 1 Low Byte
    273
    
    TH0: Timer 0 High Byte
    274
    
    TH1: Timer 1 High Byte
    274
    
    TMR2CN0: Timer 2 Control
    275
    
    TMR2RLL: Timer 2 Reload Low Byte
    276
    
    TMR2RLH: Timer 2 Reload High Byte
    276
    
    TMR2L: Timer 2 Low Byte
    276
    
    TMR2H: Timer 2 High Byte
    277
    
    TMR2CN1: Timer 2 Control 1
    278
    
    TMR3CN0: Timer 3 Control 0
    279
    
    TMR3RLL: Timer 3 Reload Low Byte
    280
    
    TMR3RLH: Timer 3 Reload High Byte
    280
    
    TMR3L: Timer 3 Low Byte
    280
    
    TMR3H: Timer 3 High Byte
    281
    
    TMR3CN1: Timer 3 Control 1
    282
    
    TMR4CN0: Timer 4 Control 0
    284
    
    TMR4RLL: Timer 4 Reload Low Byte
    285
    
    TMR4RLH: Timer 4 Reload High Byte
    285
    
    TMR4L: Timer 4 Low Byte
    285
    
    TMR4H: Timer 4 High Byte
    286
    
    TMR4CN1: Timer 4 Control 1
    287
    
    TMR5RLL: Timer 5 Reload Low Byte
    288
    
    TMR5RLH: Timer 5 Reload High Byte
    288
    
    TMR5L: Timer 5 Low Byte
    288
    
    TMR5H: Timer 5 High Byte
    289
    
    TMR5CN0: Timer 5 Control 0
    290
    
    TMR5CN1: Timer 5 Control 1
    291
20 Universal Asynchronous Receiver/Transmitter 1 (UART1)

292
- Introduction
  292
- Features
  292
- Functional Description
  293
  - Baud Rate Generation
    293
  - Data Format
    293
  - Flow Control
    294
  - Basic Data Transfer
    294
  - Data Transfer with FIFO
    294
  - Multiprocessor Communications
    297
  - LIN Break and Sync Detect
    297
  - Autobaud Detection
    297
  - Routing RX through Configurable Logic
    298
  - UART1 Control Registers
    299
    
    SCON1: UART1 Serial Port Control
    299
    
    SMOD1: UART1 Mode
    301
    
    SBUF1: UART1 Serial Port Data Buffer
    302
    
    SBCON1: UART1 Baud Rate Generator Control
    303
    
    SBRLH1: UART1 Baud Rate Generator High Byte
    303
    
    SBRLL1: UART1 Baud Rate Generator Low Byte
    304
    
    UART1FCN0: UART1 FIFO Control
    305
    
    UART1FCN1: UART1 FIFO Control
    307
    
    UART1FCT: UART1 FIFO Count
    308
    
    UART1LIN: UART1 LIN Configuration
    309
    
    UART1PCF: UART1 Configuration
    310
21 Universal Serial Bus (USB0)

311
- Introduction
  311
- Features
  311
- Functional Description
  312
  - Endpoint Addressing
    312
  - Transceiver Control
    312
  - Clock Configuration
    312
  - Register Access
    313
  - FIFO Management
    315
  - Function Addressing
    316
  - Function Configuration and Control
    317
  - Interrupts
    317
  - Serial Interface Engine
    317
  - Endpoint
    318
  - Endpoints 1, 2, and 3
    319
  - Low Energy Mode
    321
  - Charger Detect Function
    321
  - USB0 Control Registers
    326
    
    USB0XCN: USB0 Transceiver Control
    326
    
    USB0ADR: USB0 Indirect Address
    327
    
    USB0DAT: USB0 Data
    328
    
    INDEX: USB0 Endpoint Index
    328
    
    CLKREC: USB0 Clock Recovery Control
    329
    
    FIFO0: USB0 Endpoint 0 FIFO Access
    330
    
    FIFO1: USB0 Endpoint 1 FIFO Access
    330
    
    FIFO2: USB0 Endpoint 2 FIFO Access
    330
    
    FIFO3: USB0 Endpoint 3 FIFO Access
    331
    
    POWER: USB0 Power
    332
    
    FRAMEL: USB0 Frame Number Low
    333
    
    FRAMEH: USB0 Frame Number High
    333
    
    IN1INT: USB0 in Endpoint Interrupt
    334
    
    OUT1INT: USB0 out Endpoint Interrupt
    335
    
    CMINT: USB0 Common Interrupt
    336
    
    IN1IE: USB0 in Endpoint Interrupt Enable
    337
    
    OUT1IE: USB0 out Endpoint Interrupt Enable
    338
    
    CMIE: USB0 Common Interrupt Enable
    339
    
    E0CSR: USB0 Endpoint0 Control
    340
    
    E0CNT: USB0 Endpoint0 Data Count
    341
    
    EENABLE: USB0 Endpoint Enable
    342
    
    EINCSRL: USB0 in Endpoint Control Low
    343
    
    EINCSRH: USB0 in Endpoint Control High
    344
    
    EOUTCSRL: USB0 out Endpoint Control Low
    345
    
    EOUTCSRH: USB0 out Endpoint Control High
    346
    
    EOUTCNTL: USB0 out Endpoint Count Low
    346
    
    EOUTCNTH: USB0 out Endpoint Count High
    347
    
    USB0CF: USB0 Configuration
    348
    
    USB0AEC: USB0 Advanced Energy Control
    350
    
    USB0CDCF: USB0 Charger Detect Configuration
    351
    
    USB0CDCN: USB0 Charger Detect Control
    352
    
    USB0CDSTA: USB0 Charger Detect Status
    353
22 Watchdog Timer (WDT0)

355
- Introduction
  355
- Features
  355
- Using the Watchdog Timer
  355
- WDT0 Control Registers
  357
  - WDTCN: Watchdog Timer Control
    357
23 C2 Debug and Programming Interface

358
- Introduction
  358
- Features
  358
- Pin Sharing
  358
- C2 Interface Registers
  359
  - C2ADD: C2 Address
    359
  - C2DEVID: C2 Device ID
    359
  - C2REVID: C2 Revision ID
    359
  - C2FPCTL: C2 Flash Programming Control
    360
  - C2FPDAT: C2 Flash Programming Data
    360
24 Revision History

361

Silicon Laboratories EFM8 Series Programming Manual (35 pages)

Brand: Silicon Laboratories | Category: Motherboard | Size: 3 MB

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Motherboard Microcontrollers Computer Hardware Control Unit Adapter

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Silicon Laboratories EFM8 Series Manuals

Silicon Laboratories EFM8 Series Reference Manual (362 pages)

Table of Contents

1 System Overview

2 Memory

3 Special Function Registers

4 Flash Memory

5 Device Identification

6 Interrupts

7 Power Management and Internal Regulators

8 Clocking and Oscillators

9 Reset Sources and Power Supply Monitor

10 Microcontroller Core

11 Port I/O, Crossbar, External Interrupts, and Port Match

12 Analog-To-Digital Converter (ADC0)

13 Comparators (CMP0 and CMP1)

14 Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)

15 Cyclic Redundancy Check (CRC0)

16 Programmable Counter Array (PCA0)

17 Serial Peripheral Interface (SPI0)

18 System Management Bus / I2C (SMB0)

19 Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5)

20 Universal Asynchronous Receiver/Transmitter 1 (UART1)

21 Universal Serial Bus (USB0)

22 Watchdog Timer (WDT0)

23 C2 Debug and Programming Interface

24 Revision History

Silicon Laboratories EFM8 Series Programming Manual (35 pages)

Table of Contents

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