Sfr Definition 8.6. Dac1Cn: Dac1 Control - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
DAC1EN -
Bit7 Bit6
Bit7: DAC1EN: DAC1 Enable Bit.
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode.
1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational.
Bits6–5: UNUSED. Read = 00b; Write = don't care.
Bits4–3: DAC1MD1–0: DAC1 Mode Bits:
00: DAC output updates occur on a write to DAC1H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
Bits2–0: DAC1DF2: DAC1 Data Format Bits:
000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
DAC1H
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits are in DAC1L[7:1].
DAC1H
MSB
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits are in DAC1L[7:2].
DAC1H
MSB
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits are in DAC1L[7:3].
DAC1H
MSB
1xx: The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least
significant 4-bits are in DAC1L[7:4].
DAC1H
MSB
110

SFR Definition 8.6. DAC1CN: DAC1 Control

R/W R/W
- DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000
Bit5 Bit4
MSB
Rev. 1.4
R/W R/W R/W
Bit3 Bit2 Bit1
DAC1L
DAC1L
DAC1L
DAC1L
DAC1L
LSB
R/W Reset Value
Bit0
SFR Address: 0xD4
SFR Page: 1
LSB
LSB
LSB
LSB