Pinout And Package Definitions; Table 4.1. Pin Definitions - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
4.

Pinout and Package Definitions

'F120
Name
'F122
'F124
'F126
V 37,
DD
64, 90
DGND 38,
63, 89
AV+ 11, 14
AGND 10, 13
TMS 1
TCK 2
TDI 3
TDO 4
RST 5
XTAL1 26
XTAL2 27
MONEN 28

Table 4.1. Pin Definitions

Pin Numbers
'F121 'F130 'F131
Type
'F123 'F132 'F133
'F125
'F127
24, 37, 24,
41, 57 64, 90 41, 57
25, 38, 25,
40, 56 63, 89 40, 56
6 11, 14 6
5 10, 13 5
58 1 58 D In JTAG Test Mode Select with internal pullup.
59 2 59 D In JTAG Test Clock with internal pullup.
60 3 60 D In JTAG Test Data Input with internal pullup. TDI is
61 4 61 D Out JTAG Test Data Output with internal pullup. Data
62 5 62 D I/O Device Reset. Open-drain output of internal V
17 26 17 A In Crystal Input. This pin is the return for the inter-
18 27 18 A Out Crystal Output. This pin is the excitation driver
19 28 19 D In V
Description
Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Analog Ground. Must be tied to Ground.
latched on the rising edge of TCK.
is shifted out on TDO on the falling edge of TCK.
TDO output is a tri-state driver.
monitor. Is driven low when V
MONEN is high. An external source can initiate
a system reset by driving this pin low.
nal oscillator circuit for a crystal or ceramic reso-
nator. For a precision internal clock, connect a
crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
for a crystal or ceramic resonator.
Monitor Enable. When tied high, this pin
DD
enables the internal V
system reset when V
DD
low, the internal V monitor is disabled.
DD
This pin must be tied high or low.
Rev. 1.4
DD
is < V and
DD RST
monitor, which forces a
DD
is < V . When tied
RST
41