Sfr Definition 18.17. P6: Port6 Data; Sfr Definition 18.18. P6Mdout: Port6 Output Mode - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
P6.7 P6.6
Bit7 Bit6
Bits7–0: P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P6MDOUT bit = 0). See SFR Definition
18.18.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
Note: P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
Memory Interface and On-Chip XRAM" on page 219
External Memory Interface.

SFR Definition 18.18. P6MDOUT: Port6 Output Mode

R/W R/W
Bit7 Bit6
Bits7–0: P6MDOUT.[7:0]: Port6 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
256

SFR Definition 18.17. P6: Port6 Data

R/W R/W R/W
P6.5 P6.4 P6.3
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
P6.2 P6.1 P6.0
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Section "17. External Data
for more information about the
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Reset Value
11111111
Bit
Addressable
0xE8
F
Reset Value
00000000
0x9E
F