Memory Mode Selection; Internal Xram Only; Split Mode Without Bank Select; Figure 17.3. Emif Operating Modes - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

17.5. Memory Mode Selection

The external data memory space can be configured in one of four modes, shown in Figure 17.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 17.2). These modes are summarized below.
More information about the different modes can be found in
External Memory Timing Control" on page 226

17.5.1. Internal XRAM Only

When EMI0CF.[3:2] are set to '00', all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 8 k boundaries. As an
example, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.
• 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
• 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.

17.5.2. Split Mode without Bank Select

When EMI0CF.[3:2] are set to '01', the XRAM memory map is split into two areas, on-chip space and off-
chip space.
• Effective addresses below the 8 k boundary will access on-chip XRAM space.
• Effective addresses above the 8 k boundary will access off-chip space.
• 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the "No Bank Select" mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with "Split Mode with Bank Select" described below. The lower 8-bits of the Address Bus
A[7:0] are driven, determined by R0 or R1.
• 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-
chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are
driven during the off-chip transaction.
EMI0CF[3:2] = 00
0xFFFF
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
224
.
EMI0CF[3:2] = 01
0xFFFF
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0x0000

Figure 17.3. EMIF Operating Modes

Rev. 1.4
Section "SFR Definition 17.3. EMI0TC:
EMI0CF[3:2] = 10
0xFFFF
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
0x0000
EMI0CF[3:2] = 11
0xFFFF
Off-Chip
Memory
0x0000