Table 14.2. Pll Frequency Characteristics; Sfr Definition 14.8. Pll0Flt: Pll Filter - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
- - PLLICO1 PLLICO0
Bit7 Bit6
Bits 7–6: UNUSED: Read = 00b; Write = don't care.
Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:
PLL Output Clock
65–100 MHz
Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:
Divided PLL Reference Clock
12.2–19.5 MHz
7.8–12.5 MHz

Table 14.2. PLL Frequency Characteristics

–40 to +85 °C unless otherwise specified
Parameter
Input Frequency
(Divided Reference Frequency)
PLL Output Frequency
*Note: The maximum operating frequency of the C8051F124/5/6/7 is 50 MHz

SFR Definition 14.8. PLL0FLT: PLL Filter

R/W R/W
PLLLP3
Bit5 Bit4
45–80 MHz
30–60 MHz
25–50 MHz
19–30 MHz
5–8 MHz
Conditions
R/W R/W R/W
PLLLP2 PLLLP1
Bit3 Bit2 Bit1
PLLICO1-0
00
01
10
11
PLLLP3-0
0001
0011
0111
1111
Min
5
25
Rev. 1.4
R/W Reset Value
PLLLP0 00110001
Bit0
SFR Address: 0x8F
SFR Page: F
Typ Max Units
30 MHz
100* MHz
195