Enhanced Serial Peripheral Interface (Spi0); Figure 20.1. Spi Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

20. Enhanced Serial Peripheral Interface (SPI0)

The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SPI0CKR
Clock Divide
SYSCLK
SFR Bus
SPI0CFG
Logic
SPI CONTROL LOGIC
Data Path
Control
Tx Data
SPI0DAT
Transmit Data Buffer
Shift Register
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
Write
SPI0DAT
SPI0DAT
SFR Bus

Figure 20.1. SPI Block Diagram

SPI0CN
Pin Interface
Control
MOSI
C
R
SCK
O
Pin
S
Control
S
Logic
MISO
Rx Data
B
A
R
NSS
Rev. 1.4
SPI IRQ
Port I/O
273