Table 13.1. Reset Electrical Characteristics - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

Table 13.1. Reset Electrical Characteristics

–40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage Current
V for RST Output Valid
DD
AV+ for RST Output Valid
V POR Threshold (V
DD RST
Minimum RST Low Time to Gen-
erate a System Reset
Reset Time Delay
Missing Clock Detector Timeout
*Note: When operating at frequencies above 50 MHz, minimum
Conditions
I = 8.5 mA, V
OL DD
RST = 0.0 V
)*
RST rising edge after V
crosses V threshold
RST
Time from last system clock to
reset initiation
Min
= 2.7 to 3.6 V
—
0.7 x V
DD
—
—
1.0
1.0
2.40
10
DD
80
100
V
supply Voltage is 3.0 V.
DD
Rev. 1.4
Typ Max Units
— 0.6 V
— — V
0.3 x V
—
DD
50 — µA
— — V
— — V
2.55 2.70 V
— — ns
100 120 ms
220 500 µs
183