C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
SFR Definition 12.10. MAC0ACC0: MAC0 Accumulator Byte 0
R
R
Bit7
Bit6
Bits 7 – 0: Byte 0 (bits 7 – 0) of MAC0 Accumulator.
*Note:
The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.11. MAC0OVR: MAC0 Accumulator Overflow
R
R
Bit7
Bit6
Bits 7 – 0: MAC0 Accumulator Overflow Bits (bits 39 – 32).
*Note:
The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.12. MAC0RNDH: MAC0 Rounding Register High Byte
R
R
Bit7
Bit6
Bits 7 – 0: High Byte (bits 15 – 8) of MAC0 Rounding Register.
174
R
R
R
Bit5
Bit4
Bit3
R
R
R
Bit5
Bit4
Bit3
R
R
R
Bit5
Bit4
Bit3
Rev. 1.4
R
R
R
Bit2
Bit1
Bit0
SFR Address: 0x93
SFR Page: 3
R
R
R
Bit2
Bit1
Bit0
SFR Address: 0x97
SFR Page: 3
R
R
R
Bit2
Bit1
Bit0
SFR Address: 0xCF
SFR Page: 3
Reset Value
00000000
Reset Value
00000000
Reset Value
00000000
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