Sfr Definition 16.2. Cch0Tn: Cache Tuning; Sfr Definition 16.3. Cch0Lc: Cache Lock Control - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 16.2. CCH0TN: Cache Tuning

R/W R/W
CHMSCTL
Bit7 Bit6
Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1).
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first
be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition
16.4).
Bit 3: CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.
Bit 2: CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.
Bits 1–0: CHMSTH: Cache Miss Penalty Threshold.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.

SFR Definition 16.3. CCH0LC: Cache Lock Control

R/W R/W
CHPUSH CHPOP
Bit7 Bit6
Bit 7: CHPUSH: Cache Push Enable.
This bit enables cache push operations, which will lock information in cache slots using
MOVC instructions.
0: Cache push operations are disabled.
1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-
byte segment containing the data is locked into the cache at the location indicated by
CHSLOT, and CHSLOT is decremented.
Note that no more than 61 cache slots should be locked at one time, since the entire cache
will be unlocked when CHSLOT is equal to 0.
Bit 6: CHPOP: Cache Pop.
Writing a '1' to this bit will increment CHSLOT and then unlock that location. This bit always
reads '0'. Note that Cache Pop operations should not be performed while CHSLOT =
111110b. "Pop"ing more Cache slots than have been "Push"ed will have indeterminate
results on the Cache performance.
Bits 5–0: CHSLOT: Cache Slot Pointer.
These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are
locked, and will not be changed by the processor, except when CHSLOT equals 0.
216
R/W R/W R/W
CHALGM CHFIXM
Bit5 Bit4 Bit3
R R R
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W
CHMSTH
Bit2 Bit1
R R
CHSLOT
Bit2 Bit1
R/W Reset Value
00000100
Bit0
SFR Address: 0xA2
SFR Page: F
R Reset Value
00111110
Bit0
SFR Address: 0xA3
SFR Page: F