Sfr Definition 18.15. P5: Port5 Data; Sfr Definition 18.16. P5Mdout: Port5 Output Mode - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
P5.7 P5.6
Bit7 Bit6
Bits7–0: P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P5MDOUT bit = 0). See SFR Definition
18.16.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note: P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-
multiplexed mode). See
XRAM" on page 219

SFR Definition 18.16. P5MDOUT: Port5 Output Mode

R/W R/W
Bit7 Bit6
Bits7–0: P5MDOUT.[7:0]: Port5 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

SFR Definition 18.15. P5: Port5 Data

R/W R/W R/W
P5.5 P5.4 P5.3
Bit5 Bit4 Bit3
Section "17. External Data Memory Interface and On-Chip
for more information about the External Memory Interface.
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
P5.2 P5.1 P5.0
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Reset Value
11111111
Bit
Addressable
0xD8
F
Reset Value
00000000
0x9D
F
255