Sfr Definition 18.4. P0: Port0 Data; Sfr Definition 18.5. P0Mdout: Port0 Output Mode - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
R/W R/W
P0.7 P0.6
Bit7 Bit6
Bits7–0: P0.[7:0]: Port0 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory Interface.
Note:
See Section "17. External Data Memory Interface and On-Chip XRAM" on page 219
more information. See also SFR Definition 18.3 for information about configuring the Crossbar
for External Memory accesses.

SFR Definition 18.5. P0MDOUT: Port0 Output Mode

R/W R/W
Bit7 Bit6
Bits7–0: P0MDOUT.[7:0]: Port0 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note: SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
248

SFR Definition 18.4. P0: Port0 Data

R/W R/W R/W
P0.5 P0.4 P0.3
Bit5 Bit4 Bit3
R/W R/W R/W
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
P0.2 P0.1 P0.0
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Reset Value
11111111
Bit
Addressable
0x80
All Pages
for
Reset Value
00000000
0xA4
F