Sfr Definition 11.14. Eie1: Extended Interrupt Enable 1 - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 11.14. EIE1: Extended Interrupt Enable 1

R/W R/W
ECP1R ECP1F ECP0R
Bit7 Bit6
Bit7: ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt.
This bit sets the masking of the CP1 rising edge interrupt.
0: Disable CP1 rising edge interrupts.
1: Enable CP1 rising edge interrupts.
Bit6: ECP1F: Enable Comparator1 (CP1) Falling Edge Interrupt.
This bit sets the masking of the CP1 falling edge interrupt.
0: Disable CP1 falling edge interrupts.
1: Enable CP1 falling edge interrupts.
Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable CP0 rising edge interrupts.
Bit4: ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable CP0 falling edge interrupts.
Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable PCA0 interrupts.
1: Enable PCA0 interrupts.
Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable ADC0 Window Comparison Interrupt.
Bit1: ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable SMBus interrupts.
1: Enable SMBus interrupts.
Bit0: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable SPI0 interrupts.
1: Enable SPI0 interrupts.
R/W R/W R/W
ECP0F EPCA0
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W
EWADC0 ESMB0 ESPI0
Bit2 Bit1
SFR Address:
SFR Page:
R/W Reset Value
00000000
Bit0
0xE6
All Pages
159