Silicon Labs C8051F127 Manuals

Manuals and User Guides for Silicon Labs C8051F127. We have 2 Silicon Labs C8051F127 manuals available for free PDF download: Manual

Silicon Laboratories C8051F127 Manual

Silicon Laboratories C8051F127 Manual (350 pages)

8K ISP FLASH MCU

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 4 MB

Table of Contents

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Silicon Laboratories C8051F127 Manual

Silicon Laboratories C8051F127 Manual (322 pages)

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 2 MB

Table of Contents

Table of Contents
3
1 System Overview

19
2 Absolute Maximum Ratings

36
- Table 2.1. Absolute Maximum Ratings
  36
3 Global DC Electrical Characteristics

37
- Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3)
  37
- Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)
  38
4 Pinout and Package Definitions

39
5 Adc0 (12-Bit Adc, C8051F120/1/4/5 Only)

49
6 Adc0 (10-Bit Adc, C8051F122/3/6/7 Only)

67
7 Adc2 (8-Bit Adc)

85
8 Dacs, 12-Bit Voltage Mode

99
9 Voltage Reference (C8051F120/2/4/6)

107
10 Voltage Reference (C8051F121/3/5/7)

109
11 Comparators

111
12 Microcontroller

119
- Figure 12.1. CIP-51 Block Diagram
  119
- Instruction Set
  120
- Memory Organization
  125
- Interrupt Handler
  146
- Power Management Modes
  155
  - Idle Mode
    155
  - Stop Mode
    155
  - Figure 12.27. PCON: Power Control
    156
13 Multiply and Accumulate (Mac0)

157
14 Reset Sources

167
- Figure 14.1. Reset Sources
  167
- External Reset
  168
- Figure 14.2. Reset Timing
  168
- Power-Fail Reset
  168
- Power-On Reset
  168
- Comparator0 Reset
  169
- External CNVSTR0 Pin Reset
  169
- Missing Clock Detector Reset
  169
- Watchdog Timer Reset
  169
  - Enable/Reset WDT
    169
  - Disable WDT
    170
  - Disable WDT Lockout
    170
  - Setting WDT Interval
    170
  - Figure 14.3. WDTCN: Watchdog Timer Control Register
    170
  - Figure 14.4. RSTSRC: Reset Source Register
    171
  - Table 14.1.Reset Electrical Characteristics
    172
15 Oscillators

173
16 Flash Memory

185
17 Branch Target Cache

193
18 External Data Memory Interface and On-Chip Xram

199
19 Port Input/Output

215
20 System Management Bus / I2C Bus (Smbus0)

237
- Figure 20.1. Smbus0 Block Diagram
  237
- Smbus Protocol
  238
  - Figure 20.2. Typical Smbus Configuration
    238
  - Arbitration
    239
  - Clock Low Extension
    239
  - Figure 20.3. Smbus Transaction
    239
  - SCL High (Smbus Free) Timeout
    239
  - SCL Low Timeout
    239
- Supporting Documents
  238
- Smbus Transfer Modes
  240
- Smbus Special Function Registers
  242
  - Control Register
    242
  - Figure 20.8. SMB0CN: Smbus0 Control Register
    243
  - Clock Rate Register
    244
  - Figure 20.9. SMB0CR: Smbus0 Clock Rate Register
    244
  - Data Register
    245
  - Address Register
    245
  - Figure 20.10. SMB0DAT: Smbus0 Data Register
    245
  - Figure 20.11. SMB0ADR: Smbus0 Address Register
    245
  - Status Register
    246
  - Figure 20.12. SMB0STA: Smbus0 Status Register
    246
  - Table 20.1.SMB0STA Status Codes and States
    247
21 Enhanced Serial Peripheral Interface (Spi0)

249

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