Frame And Transmission Error Detection; Figure 21.7. Uart Multi-Processor Mode Interconnect Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Master
Device
RX TX

Figure 21.7. UART Multi-Processor Mode Interconnect Diagram

21.3. Frame and Transmission Error Detection

All Modes:
The Transmit Collision bit (TXCOL0 bit in register SSTA0) reads '1' if user software writes data to the
SBUF0 register while a transmit is in progress.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SSTA0) reads '1' if a new data byte is latched into the receive
buffer before software has read the previous byte. The Frame Error bit (FE0 in register SSTA0) reads '1' if
an invalid (low) STOP bit is detected.
294
Slave Slave
Device Device
RX TX RX
Rev. 1.4
Slave
Device
TX RX TX
+5V