Figure 18.2. Port I/O Functional Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
A wide array of digital resources is available through the four lower I/O Ports: P0, P1, P2, and P3. Each of
the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled
by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 18.2. The system
designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that
the state of a Port I/O pin can always be read from its associated Data register regardless of whether that
pin has been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as
Analog Inputs to ADC2.
An External Memory Interface which is active during the execution of an off-chip MOVX instruction can be
active on either the lower Ports or the upper Ports. See
and On-Chip XRAM" on page 219
2
Highest
UART0
Priority
4
SPI
2
SMBus
2
UART1
7
PCA
2
Comptr.
Outputs
T0, T1,
T2, T2EX,
8
T4,T4EX
/INT0,
/INT1
Lowest /SYSCLK divided by 1,2,4, or 8
Priority
2
CNVSTR0/2
8
P0
(P0.0-P0.7)
8
P1
(P1.0-P1.7)
Port
8
Latches
P2
(P2.0-P2.7)
8
P3
(P3.0-P3.7)

Figure 18.2. Port I/O Functional Block Diagram

Section "17. External Data Memory Interface
for more information about the External Memory Interface.
XBR0, XBR1,
XBR2, P1MDIN
Registers
Priority
Decoder
Digital
Crossbar
To External
Memory
Interface
(EMIF)
Rev. 1.4
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
P0
8
I/O
Cells
P1
8
I/O
Cells
P2
8
I/O
Cells
P3
8
I/O
Cells
To ADC2 Input
('F12x Only)
External
Pins
P0.0
Highest
Priority
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
Lowest
Priority
P3.7
237