8-Bit Pulse Width Modulator Mode; Figure 24.8. Pca 8-Bit Pwm Mode Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

24.2.5. 8-Bit Pulse Width Modulator Mode

Each module can be used independently to generate pulse width modulated (PWM) outputs on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be
low (see Figure 24.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) with-
out software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit
Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 24.2.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to '0'; writing to PCA0CPHn sets ECOMn to '1'.
PCA0CPMn
P P
E C C M T E
W W
C A A A O C
M M
O P P T G C
1 n
M P N n n F
6
n n n n
n
0 0 0 0 0 0
Enable
PCA Timebase
Equation 24.2. 8-Bit PWM Duty Cycle
(
-------------------------------------------------- -
DutyCycle =
PCA0CPHn
PCA0CPLn
8-bit
match
Comparator
PCA0L
Overflow

Figure 24.8. PCA 8-Bit PWM Mode Diagram

)
256 PCA0CPHn –
256
CEXn
SET
S Q
R Q
CLR
Rev. 1.4
Crossbar Port I/O
333