Figure 1.1. C8051F120/124 Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
VDD
VDD
VDD
Digital Power
DGND
DGND
DGND
AV+
AV+
Analog Power
AGND
AGND
TCK
Boundary Scan
JTAG
TMS
TDI Logic
Debug HW
TDO
RST
VDD
WDT
MONEN
Monitor
External Oscillator
XTAL1
Circuit
XTAL2
PLL
Circuitry
Calibrated Internal
Oscillator
VREF
VREF
VREFD
DAC1
DAC1
(12-Bit)
DAC0
DAC0
(12-Bit)
VREF0
AIN0.0
AIN0.1
AIN0.2
A
AIN0.3
M
Prog
AIN0.4
Gain
U
AIN0.5
X
AIN0.6
AIN0.7
TEMP
SENSOR
CP0+
CP0
CP0-
CP1+
CP1
CP1-
SFR Bus
8
256 byte
0
RAM
5
8 kB
Reset
XRAM
1
External Data
Memory Bus
C
System
Clock
o
128 kB
FLASH
r
e
64x4 byte
cache
ADC
100 ksps
(12-Bit)

Figure 1.1. C8051F120/124 Block Diagram

Port I/O
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
ADC
500 ksps
(8-Bit)
C
Bus Control
T
L
A
Address Bus
d
d
r
D
Data Bus
a
t
a
Rev. 1.4
P0.0
P0
Drv
P0.7
C
R
P1.0/AIN2.0
P1
O
Drv
P1.7/AIN2.7
S
S
P2.0
P2
B
Drv
P2.7
A
R
P3.0
P3
Drv
P3.7
VREF2
A
8:1
M
Prog
Gain U
X
P4.0
P4 Latch
P4
P4.4
P4.5/ALE
DRV
P4.6/RD
P4.7/WR
P5.0/A8
P5 Latch
P5
DRV
P5.7/A15
P6.0/A0
P6 Latch
P6
DRV
P6.7/A7
P7.0/D0
P7 Latch
P7
DRV
P7.7/D7
21