Figure 20.10. Spi Slave Timing (Ckpha = 0); Figure 20.11. Spi Slave Timing (Ckpha = 1) - Silicon Laboratories C8051F12 Series Manual

8k isp flash mcu
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C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
NSS
T
SE
SCK*
MOSI
T
SEZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 20.10. SPI Slave Timing (CKPHA = 0)

NSS
T
SE
SCK*
MOSI
T
SEZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.

Figure 20.11. SPI Slave Timing (CKPHA = 1)

284
T
CKL
T
CKH
T
SIS
T
SOH
T
CKL
T
CKH
T
T
SIS
SIH
T
SOH
Rev. 1.4
T
SIH
T
SLH
T
SD
T
SDZ
T
SD
T
SDZ

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