Enable/Reset Wdt; Disable Wdt; Disable Wdt Lockout; Setting Wdt Interval - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in SFR Definition 13.1.

13.7.1. Enable/Reset WDT

The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-
tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.

13.7.2. Disable WDT

Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT:
CLR EA
MOV WDTCN,#0DEh
MOV WDTCN,#0ADh
SETB EA
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. This means that the prefetch engine should be enabled and interrupts should be disabled during
this procedure to avoid any delay between the two writes.

13.7.3. Disable WDT Lockout

Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always
intending to use the watchdog should write 0xFF to WDTCN in the initialization code.

13.7.4. Setting WDT Interval

WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
[ ]
3 + WDTCN 2 0 –
×
4 T
sysclk
For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be
logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads
111b after a system reset.
180
; disable all interrupts
; disable software watchdog timer
; re-enable interrupts
; where T is the system clock period.
sysclk
Rev. 1.4