Additional Features; Figure 1.7. On-Board Clock And Reset - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

1.1.3. Additional Features

Several key enhancements are implemented in the CIP-51 core and peripherals to improve overall perfor-
mance and ease of use in end applications.
The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the stan-
dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput. The extra inter-
rupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board V
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input
pin, and the RST pin. The RST pin is bi-directional, accommodating an external reset, or allowing the inter-
nally generated POR to be output on the RST pin. Each reset source except for the V
Input pin may be disabled by the user in software; the V
pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU ini-
tialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter-
nal crystal source, while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally,
an on-chip PLL is provided to achieve higher system clock speeds for increased throughput.
(Port I/O)
Crossbar
Comparator0
CP0+
CP0-
Internal
Clock
Generator
PLL
Circuitry
XTAL1
OSC
XTAL2
28
V
DD
CNVSTR
(CNVSTR
reset
enable)
+
-
(CP0
reset
enable)
Missing
Clock
Detector
(one-
shot)
EN
System
Clock
CIP-51
Microcontroller
Core
Clock Select
Extended Interrupt
Handler

Figure 1.7. On-Board Clock and Reset

Rev. 1.4
monitor, a Watchdog Timer, a missing
DD
monitor is enabled/disabled via the MONEN
DD
Supply
Monitor
Supply
+
Reset
-
Timeout
WDT
EN PRE
Software Reset
System Reset
monitor and Reset
DD
RST
(wired-OR)
Reset
Funnel