Sfr Definition 20.3. Spi0Ckr: Spi0 Clock Rate; Sfr Definition 20.4. Spi0Dat: Spi0 Data - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate

R/W R/W
SCR7 SCR6
Bit7 Bit6
Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
------------------------- -
f =
× (
SCK
2 4 + 1
f = 200kHz
SCK
R/W R/W
Bit7 Bit6
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
282
R/W R/W
SCR5 SCR4 SCR3
Bit5 Bit4
---------------------------------------------- -
f =
×
SCK
2
)

SFR Definition 20.4. SPI0DAT: SPI0 Data

R/W R/W
Bit5 Bit4
Rev. 1.4
R/W R/W R/W
SCR2 SCR1
Bit3 Bit2 Bit1
SYSCLK
( )
SPI0CKR + 1
R/W R/W R/W
Bit3 Bit2 Bit1
R/W Reset Value
SCR0 00000000
Bit0
SFR Address: 0x9D
SFR Page: 0
R/W Reset Value
00000000
Bit0
SFR Address: 0x9B
SFR Page: 0