Dacs, 12-Bit Voltage Mode (C8051F12X Only); Dac Output Scheduling; Figure 8.1. Dac Functional Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
8.

DACs, 12-Bit Voltage Mode (C8051F12x Only)

The C8051F12x devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs).
Each DAC has an output swing of 0 V to (VREF-1LSB) for a corresponding input code range of 0x000 to
0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN and
DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC supply
current falls to 1 µA or less. The voltage reference for each DAC is supplied at the VREFD pin
(C8051F120/2/4/6 devices) or the VREF pin (C8051F121/3/5/7 devices). Note that the VREF pin on
C8051F121/3/5/7 devices may be driven by the internal voltage reference or an external source. If the
internal voltage reference is used it must be enabled in order for the DAC outputs to be valid. See
"9. Voltage Reference" on page 113
DACs.
8.1.

DAC Output Scheduling

Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and
supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0,
but DAC1 operation is identical.
DAC0EN
DAC0MD1
DAC0MD0
DAC0DF2
DAC0DF1
DAC0DF0
DAC1EN
DAC1MD1
DAC1MD0
DAC1DF2
DAC1DF1
DAC1DF0
for more information on configuring the voltage reference for the
REF
8 8
12
8 8
REF
8 8
12
8 8

Figure 8.1. DAC Functional Block Diagram

DAC0
AGND
DAC1
AGND
Rev. 1.4
Section
AV+
DAC0
AV+
DAC1
105