Figure 18.5. Priority Crossbar Decode Table (Emifle = 1; Emif In Non-Multiplexed Mode; P1Mdin = 0Xff) - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
P0
PIN I/O 0 1 2 3 4 5 6
TX0 ●
RX0 ●
SCK ● ●
● ●
MISO
● ●
MOSI
● ●
NSS
SDA ● ● ● ● ●
SCL ● ● ● ●
TX1 ● ● ● ● ●
● ● ● ●
RX1
● ● ● ● ●
CEX0
● ● ● ●
CEX1
CEX2 ● ● ●
CEX3 ● ●
CEX4 ●
●
CEX5
● ● ● ● ● ●
ECI
● ● ● ● ● ●
CP0
CP1 ● ● ● ● ● ●
T0 ● ● ● ● ● ●
/INT0 ● ● ● ● ● ●
● ● ● ● ● ●
T1
● ● ● ● ● ●
/INT1
● ● ● ● ● ●
T2
T2EX ● ● ● ● ● ●
T4 ● ● ● ● ● ●
T4EX ● ● ● ● ● ●
● ● ● ● ● ●
/SYSCLK
● ● ● ● ● ●
CNVSTR0
● ● ● ● ● ●
CNVSTR2
Figure 18.5. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Non-Multiplexed
242
P1
7 0 1 2 3 4 5 6 7 0 1
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
●
● ●
● ● ●
● ● ● ●
● ● ● ● ●
● ● ● ● ● ●
● ● ● ● ● ● ●
● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
AIN2 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L
Mode; P1MDIN = 0xFF)
Rev. 1.4
P2 P3
2 3 4 5 6 7 0 1 2 3 4
Muxed Data/Non-muxed Data
Crossbar Register Bits
5 6 7
UART0EN: XBR0.2
SPI0EN: XBR0.1
SMB0EN: XBR0.0
UART1EN: XBR2.2
PCA0ME: XBR0.[5:3]
ECI0E: XBR0.6
CP0E: XBR0.7
CP1E: XBR1.0
T0E: XBR1.1
INT0E: XBR1.2
T1E: XBR1.3
INT1E: XBR1.4
T2E: XBR1.5
T2EXE: XBR1.6
T4E: XBR2.3
T4EXE: XBR2.4
SYSCKE: XBR1.7
CNVSTE0: XBR2.0
CNVSTE2: XBR2.5