Uart0; Figure 21.1. Uart0 Block Diagram - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

21. UART0

UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0
may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor commu-
nication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception
of a second incoming data byte before software has finished reading the previous data byte. A Receive
Overrun bit indicates when new received data is latched into the receive buffer before the previously
received byte has been read.
UART0 is accessed via its associated SFR's, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The
single SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses
the Receive register and writing SCON0 accesses the Transmit register.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit
Interrupt flag, TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt
flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared
by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by soft-
ware. This allows software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Write to
SBUF0
SSTA0
F R T S S S S S
E X X M 0 0 0 0
0 O C O T T R R
V O D C C C C
0 L 0 L L L L
0 K K K K
1 1 1 1
UART0
Baud Rate Generation
Logic
SFR Bus
TB80
SET
SBUF0
D Q
CLR
Zero Detector
Shift
Stop Bit
Gen.
Tx Control
Start
Tx Clock
Tx IRQ
SCON0
S S S R T R T R
M M M E B B I I
0 1 2 N 8 8 0 0
0 0 0 0 0 0
EN Rx IRQ
Rx Clock
Rx Control
Start
Shift 0x1FF
Frame Error Input Shift Register
Detection (9 bits)
Load
SBUF0
SBUF0 Match Detect
Read
SBUF0
SFR Bus

Figure 21.1. UART0 Block Diagram

Rev. 1.4
TX0
Crossbar
Data
Send
TI0
Serial Port
(UART0) Interrupt
RI0
Load
SBUF
Address
Match
RB80
SADDR0
SADEN0
RX0
Crossbar
Port I/O
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