Smbus Transfer Modes; Master Transmitter Mode; Master Receiver Mode; Figure 19.4. Typical Master Transmitter Sequence - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

19.3. SMBus Transfer Modes

The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the
interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave
Transmitter, or Slave Receiver. See Table 19.1 for transfer mode status decoding using the SMB0STA sta-
tus register. The following mode descriptions illustrate an interrupt-driven SMBus0 application; SMBus0
may alternatively be operated in polled mode.

19.3.1. Master Transmitter Mode

Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START
condition and then transmits the first byte containing the address of the target slave device and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ACK) from the
slave after each byte. To indicate the end of the serial transfer, SMBus0 generates a STOP condition.
S SLA
Interrupt
Received by SMBus
Interface
Transmitted by
SMBus Interface

Figure 19.4. Typical Master Transmitter Sequence

19.3.2. Master Receiver Mode

Serial data is received on SDA while the serial clock is output on SCL. The SMBus0 interface generates a
START followed by the first data byte containing the address of the target slave and the data direction bit.
In this case the data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 inter-
face receives serial data from the slave and generates the clock on SCL. After each byte is received,
SMBus0 generates an ACK or NACK depending on the state of the AA bit in register SMB0CN. SMBus0
generates a STOP condition to indicate the end of the serial transfer.
S
Interrupt
Received by SMBus
Interface
Transmitted by
SMBus Interface

Figure 19.5. Typical Master Receiver Sequence

262
W A Data Byte
Interrupt
SLA R A Data Byte
Interrupt
Rev. 1.4
A Data Byte A
Interrupt Interrupt
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
A Data Byte N
Interrupt Interrupt
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
P
P