Sfr Definition 14.3. Clksel: System Clock Selection - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 14.3. CLKSEL: System Clock Selection

R/W R/W
- -
Bit7 Bit6
Bits 7–6: Reserved.
Bits 5–4: CLKDIV1–0: Output SYSCLK Divide Factor.
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See Section "18. Port Input/Output" on page 235
put to a port pin.
Bits 3–2: Reserved.
Bits 1–0: CLKSL1–0: System Clock Source Select Bits.
00: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in
OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the PLL.
11: Reserved.
188
R/W R/W
CLKDIV1 CLKDIV0
Bit5 Bit4
Rev. 1.4
R/W R/W R/W
- - CLKSL1
Bit3 Bit2 Bit1
for more details about routing this out-
R/W Reset Value
CLKSL0 00000000
Bit0
SFR Address: 0x97
SFR Page: F