Memory Organization; Program Memory; Figure 11.2. Memory Map - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

11.2. Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 128k bytes (C8051F12x and C8051F130/1) or 64k bytes (C8051F132/3) of internal program
memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in
Figure 11.2.
PROGRAM/DATA MEMORY
(FLASH)
C8051F120/1/2/3/4/5/6/7
C8051F130/1
0x200FF
Scrachpad Memory
(DATA only)
0x20000
0x1FFFF
RESERVED
0x1FC00
0x1FBFF
Programmable in 1024
Byte Sectors)
0x00000
C8051F132/3
0x200FF
Scrachpad Memory
(DATA only)
0x20000
0x0FFFF
Programmable in 1024
Byte Sectors)
0x00000

11.2.1. Program Memory

The C8051F12x and C8051F130/1 have a 128 kB program memory space. The MCU implements this pro-
gram memory space as in-system re-programmable Flash memory in four 32 kB code banks. A common
code bank (Bank 0) of 32 kB is always accessible from addresses 0x0000 to 0x7FFF. The three upper
code banks (Bank 1, Bank 2, and Bank 3) are each mapped to addresses 0x8000 to 0xFFFF, depending
on the selection of bits in the PSBANK register, as described in SFR Definition 11.1. The IFBANK bits
select which of the upper banks are used for code execution, while the COBANK bits select the bank to be
used for direct writes and reads of the Flash memory. Note: 1024 bytes of the memory in Bank 3
(0x1FC00 to 0x1FFFF) are reserved and are not available for user program or data storage. The
C8051F132/3 have a 64k byte program memory space implemented as in-system re-programmable Flash
memory, and organized in a contiguous block from address 0x00000 to 0x0FFFF.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to
Upper 128 RAM
(Indirect Addressing
(Direct and Indirect
FLASH
Bit Addressable
(In-System
General Purpose
FLASH
(In-System

Figure 11.2. Memory Map

Section "15. Flash Memory" on page 199
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Special Function
Registers
Only) (Direct Addressing Only)
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
Registers
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Off-chip XRAM space
0x2000
0x1FFF
XRAM - 8192 Bytes
(accessable using MOVX
instruction)
0x0000
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