Sfr Definition 12.4. Mac0Al: Mac0 A Low Byte; Sfr Definition 12.5. Mac0Bh: Mac0 B High Byte; Sfr Definition 12.6. Mac0Bl: Mac0 B Low Byte - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3

SFR Definition 12.4. MAC0AL: MAC0 A Low Byte

R R
Bit7 Bit6
Bits 7 – 0: Low Byte (bits 7 – 0) of MAC0 A Register.

SFR Definition 12.5. MAC0BH: MAC0 B High Byte

R R
Bit7 Bit6
Bits 7 – 0: High Byte (bits 15 – 8) of MAC0 B Register.

SFR Definition 12.6. MAC0BL: MAC0 B Low Byte

R R
Bit7 Bit6
Bits 7 – 0: Low Byte (bits 7 – 0) of MAC0 B Register.
A write to this register initiates a Multiply or Multiply and Accumulate operation.
*Note: The contents of this register should not be changed by software during the first MAC0 pipeline stage.
172
R R R
Bit5 Bit4 Bit3
R R R
Bit5 Bit4 Bit3
R R R
Bit5 Bit4 Bit3
Rev. 1.4
R R R
Bit2 Bit1 Bit0
SFR Address: 0xC1
SFR Page: 3
R R R
Bit2 Bit1 Bit0
SFR Address: 0x92
SFR Page: 3
R R R
Bit2 Bit1 Bit0
SFR Address: 0x91
SFR Page: 3
Reset Value
00000000
Reset Value
00000000
Reset Value
00000000