Sfr Definition 14.1. Oscicl: Internal Oscillator Calibration; Sfr Definition 14.2. Oscicn: Internal Oscillator Control - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Electrical specifications for the precision internal oscillator are given in Table 14.1. Note that the system
clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the
IFCN bits in register OSCICN.

SFR Definition 14.1. OSCICL: Internal Oscillator Calibration.

R/W R/W
Bit7 Bit6
Bits 7–0: OSCICL: Internal Oscillator Calibration Register.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the
internal oscillator base frequency. The reset value is factory calibrated to generate an inter-
nal oscillator frequency of 24.5 MHz.

SFR Definition 14.2. OSCICN: Internal Oscillator Control

R/W R
IOSCEN IFRDY
Bit7 Bit6
Bit 7: IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
Bit 6: IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator not running at programmed frequency.
1: Internal Oscillator running at programmed frequency.
Bits 5–2: Reserved.
Bits 1–0: IFCN1-0: Internal Oscillator Frequency Control Bits.
00: Internal Oscillator is divided by 8.
01: Internal Oscillator is divided by 4.
10: Internal Oscillator is divided by 2.
11: Internal Oscillator is divided by 1.
186
R/W R/W R/W
Bit5 Bit4 Bit3
R/W R R/W
- - -
Bit5 Bit4 Bit3
Rev. 1.4
R/W R/W R/W
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
R/W R/W R/W
- IFCN1 IFCN0
Bit2 Bit1 Bit0
SFR Address:
SFR Page:
Reset Value
Variable
0x8B
F
Reset Value
11000000
0x8A
F