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C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
19. System Management Bus / I2C Bus (SMBus0)
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus0 interface autonomously con-
trolling the serial transfer of the data. A method of extending the clock-low duration is available to accom-
modate devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation.
SMB0CN
B
E
S
S
S
A
F
T
U
N
T
T
I
A
T
O
S
S
A
O
E
E
Y
M
B
SMBUS
Interrupt
Request
IRQ
B
A
B
7
S
S
S
S
S
S
S
L
L
L
L
L
L
L
V
V
V
V
V
V
V
G
6
5
4
3
2
1
0
C
SMB0ADR
SFR Bus
SFR Bus
SMB0STA
SMB0CR
S
S
S
S
S
S
S
S
C
C
C
C
T
T
T
T
T
T
T
T
R
R
R
R
A
A
A
A
A
A
A
A
7
6
5
4
7
6
5
4
3
2
1
0
Clock Divide
Logic
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
Data Path
Control
A
0000000b
7 MSBs
8
SMB0DAT
7
6
5
4
3
2
1
0
8
8
Read
Write to
SMB0DAT
SMB0DAT
Figure 19.1. SMBus0 Block Diagram
C
C
C
C
R
R
R
R
3
2
1
0
SYSCLK
FILTER
SCL
N
Control
SDA
Control
FILTER
1
N
0
Rev. 1.4
SCL
C
R
O
S
Port I/O
S
B
A
R
SDA
259
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