Extest Instruction; Sample Instruction; Bypass Instruction; Idcode Instruction - Silicon Laboratories C8051F12 Series Manual

C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Table 25.1. Boundary Data Register Bit Definitions (Continued)
Bit Action
103, 105, 107, Capture P6.n input from pin
109, 111, 113, 115,
Update
117
118, 120, 122, Capture P7.n output enable from MCU
124, 126, 128,
Update
130, 132
119, 121, 123, Capture P7.n input from pin
125, 127, 129,
Update
131, 133

25.1.1. EXTEST Instruction

The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.

25.1.2. SAMPLE Instruction

The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.

25.1.3. BYPASS Instruction

The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.

25.1.4. IDCODE Instruction

The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.

JTAG Register Definition 25.2. DEVICEID: JTAG Device ID

Version
Bit31 Bit28 Bit27
Version = 0000b
Part Number = 0000 0000 0000 0111b (C8051F120/1/2/3/4/5/6/7 or C8051F130/1/2/3)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Target
P6.n output to pin
P7.n output enable to pin
P7.n output to pin
Part Number
Bit12 Bit11
Rev. 1.4
Manufacturer ID
Bit1
Reset Value
1 0xn0003243
Bit0
343